punt Blackfin VDSP headers and import sanitized/auto-generated ones

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

10 files changed, 86 insertions, 79 deletions

diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
index 299cdbae73..cdf4dc69ba 100644
--- a/board/bf533-ezkit/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -286,9 +286,9 @@ int write_flash(long nOffset, int nValue)
 	long addr;
 
 	addr = (CFG_FLASH_BASE + nOffset);
-	sync();
+	SSYNC();
 	*(unsigned volatile short *)addr = nValue;
-	sync();
+	SSYNC();
 	if (poll_toggle_bit(nOffset) < 0)
 		return FLASH_FAIL;
 	return FLASH_SUCCESS;
@@ -301,9 +301,9 @@ int read_flash(long nOffset, int *pnValue)
 
 	if (nOffset != 0x2)
 		reset_flash();
-	sync();
+	SSYNC();
 	nValue = *(volatile unsigned short *)addr;
-	sync();
+	SSYNC();
 	*pnValue = nValue;
 	return TRUE;
 }
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 69e425bf97..af035976ff 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -76,9 +76,9 @@ void swap_to(int device_id)
 
 	if (device_id == ETHERNET) {
 		*pFIO_DIR = PF0;
-		sync();
+		SSYNC();
 		*pFIO_FLAG_S = PF0;
-		sync();
+		SSYNC();
 	} else if (device_id == FLASH) {
 		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
 		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@@ -88,7 +88,7 @@ void swap_to(int device_id)
 		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
-		sync();
+		SSYNC();
 	} else {
 		printf("Unknown bank to switch\n");
 	}
@@ -155,15 +155,15 @@ void cf_outb(unsigned char val, volatile unsigned char *addr)
 	 */
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	*(addr) = val;
-	sync();
+	SSYNC();
 
 	/* Setback PF1 PF0 to 0 0 to address external
 	 * memory banks  */
 	*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 unsigned char cf_inb(volatile unsigned char *addr)
@@ -172,13 +172,13 @@ unsigned char cf_inb(volatile unsigned char *addr)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	c = *(addr);
-	sync();
+	SSYNC();
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 
 	return c;
 }
@@ -189,15 +189,15 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(sect_buf + i) = *(addr);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 
 void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -206,15 +206,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	sync();
+	SSYNC();
 
 	for (i = 0; i < words; i++) {
 		*(addr) = *(sect_buf + i);
-		sync();
+		SSYNC();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	sync();
+	SSYNC();
 }
 #endif
 
@@ -235,7 +235,7 @@ void stamp_led_set(int LED1, int LED2, int LED3)
 		*pFIO_FLAG_S = PF4;
 	else
 		*pFIO_FLAG_C = PF4;
-	sync();
+	SSYNC();
 }
 
 void show_boot_progress(int status)
diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c
index d30750faa3..15141cf743 100644
--- a/board/bf533-stamp/spi.c
+++ b/board/bf533-stamp/spi.c
@@ -4,6 +4,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
 
 #if defined(CONFIG_SPI)
 
@@ -153,7 +154,7 @@ void SendSingleCommand(const int iCommand)
 
 	/*sends the actual command to the SPI TX register */
 	*pSPI_TDBR = iCommand;
-	sync();
+	SSYNC();
 
 	/*The SPI status register will be polled to check the SPIF bit */
 	Wait_For_SPIF();
@@ -174,7 +175,7 @@ void SetupSPI(const int spi_setting)
 	*pSPI_FLG = 0xFB04;
 	*pSPI_BAUD = CONFIG_SPI_BAUD;
 	*pSPI_CTL = spi_setting;
-	sync();
+	SSYNC();
 }
 
 void SPI_OFF(void)
@@ -183,7 +184,7 @@ void SPI_OFF(void)
 	*pSPI_CTL = 0x0400;	/* disable SPI */
 	*pSPI_FLG = 0;
 	*pSPI_BAUD = 0;
-	sync();
+	SSYNC();
 	udelay(CONFIG_CCLK_HZ / 50000000);
 
 }
@@ -241,10 +242,10 @@ char ReadStatusRegister(void)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
 
 	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the data has been sent */
 	status_register = *pSPI_RDBR;	/*read the status register */
 
@@ -305,18 +306,18 @@ ERROR_CODE EraseBlock(int nBlock)
 	/* Send the erase block command to the flash followed by the 24 address  */
 	/* to point to the start of a sector. */
 	*pSPI_TDBR = SPI_SE;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();
 	ShiftValue = (ulSectorOff >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulSectorOff >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulSectorOff;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/*Turns off the SPI */
@@ -351,25 +352,25 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
 
 	*pSPI_TDBR = SPI_READ;	/* Send the read command to SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 16);	/* Send the highest byte of the 24 bit address at first */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	ShiftValue = (ulStart >> 8);	/* Send the middle byte of the 24 bit address  at second */
 	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 	*pSPI_TDBR = ulStart;	/* Send the lowest byte of the 24 bit address finally */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/* Wait until the instruction has been sent */
 
 	/* After the SPI device address has been placed on the MOSI pin the data can be */
 	/* received on the MISO pin. */
 	for (i = 0; i < lCount; i++) {
 		*pSPI_TDBR = 0;	/*send dummy */
-		sync();
+		SSYNC();
 		while (!(*pSPI_STAT & RXS)) ;
 		*cnData++ = *pSPI_RDBR;	/*read  */
 
@@ -406,26 +407,26 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 		/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
 		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turns the SPI on */
 	*pSPI_TDBR = SPI_PP;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 16);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = (ulStartAddr >> 8);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	ulWAddr = ulStartAddr;
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
 	/* and sent to the SPI device. */
 	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
 		iData = *temp;
 		*pSPI_TDBR = iData;
-		sync();
+		SSYNC();
 		Wait_For_SPIF();	/*wait until the instruction has been sent */
 		temp++;
 	}
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
index 6954b3003d..d279817bba 100644
--- a/board/bf537-stamp/bf537-stamp.c
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <net.h>
 #include "ether_bf537.h"
+#include <asm/mach-common/bits/bootrom.h>
 
 /**
  * is_valid_ether_addr - Determine if the given Ethernet address is valid
@@ -117,7 +118,7 @@ int checkboard(void)
 void cf_outb(unsigned char val, volatile unsigned char *addr)
 {
 	*(addr) = val;
-	sync();
+	SSYNC();
 }
 
 unsigned char cf_inb(volatile unsigned char *addr)
@@ -125,7 +126,7 @@ unsigned char cf_inb(volatile unsigned char *addr)
 	volatile unsigned char c;
 
 	c = *(addr);
-	sync();
+	SSYNC();
 
 	return c;
 }
@@ -136,7 +137,7 @@ void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 
 	for (i = 0; i < words; i++)
 		*(sect_buf + i) = *(addr);
-	sync();
+	SSYNC();
 }
 
 void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
@@ -145,7 +146,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 	for (i = 0; i < words; i++)
 		*(addr) = *(sect_buf + i);
-	sync();
+	SSYNC();
 }
 #endif				/* CONFIG_BFIN_IDE */
 
diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c
index 36c1536e39..6c514c6609 100644
--- a/board/bf537-stamp/ether_bf537.c
+++ b/board/bf537-stamp/ether_bf537.c
@@ -30,6 +30,10 @@
 #include <malloc.h>
 #include "ether_bf537.h"
 
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/emac.h>
+#include <asm/mach-common/bits/pll.h>
+
 #ifdef CONFIG_POST
 #include <post.h>
 #endif
@@ -364,7 +368,7 @@ int SetupSystemRegs(int *opmode)
 	u16 sysctl, phydat;
 	int count = 0;
 	/* Enable PHY output */
-	*pVR_CTL |= PHYCLKOE;
+	*pVR_CTL |= CLKBUFOE;
 	/* MDC  = 2.5 MHz */
 	sysctl = SET_MDCDIV(24);
 	/* Odd word alignment for Receive Frame DMA word */
diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c
index ed85841479..8252c42fd8 100644
--- a/board/bf537-stamp/flash.c
+++ b/board/bf537-stamp/flash.c
@@ -255,7 +255,7 @@ int write_flash(long nOffset, int nValue)
 
 	addr = (CFG_FLASH_BASE + nOffset);
 	*(unsigned volatile short *)addr = nValue;
-	sync();
+	SSYNC();
 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 	if (icache_status())
 		udelay(CONFIG_CCLK_HZ / 1000000);
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
index f95b584b31..6ff0f4f96c 100644
--- a/board/bf537-stamp/nand.c
+++ b/board/bf537-stamp/nand.c
@@ -64,13 +64,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
 	this->IO_ADDR_R = this->IO_ADDR_W;
 
 	/* Drain the writebuffer */
-	sync();
+	SSYNC();
 }
 
 int bfin_device_ready(struct mtd_info *mtd)
 {
 	int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
-	sync();
+	SSYNC();
 	return ret;
 }
 
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index 60393505a2..fa119919b3 100644
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -104,15 +104,15 @@ void post_init_uart(int sclk)
 
 	*pUART_GCTL = 0x00;
 	*pUART_LCR = 0x83;
-	sync();
+	SSYNC();
 	*pUART_DLL = (divisor & 0xFF);
-	sync();
+	SSYNC();
 	*pUART_DLH = ((divisor >> 8) & 0xFF);
-	sync();
+	SSYNC();
 	*pUART_LCR = 0x03;
-	sync();
+	SSYNC();
 	*pUART_GCTL = 0x01;
-	sync();
+	SSYNC();
 }
 
 void post_out_buff(char *buff)
@@ -124,7 +124,7 @@ void post_out_buff(char *buff)
 	while ((buff[i] != '\0') && (i != 100)) {
 		while (!(*pUART_LSR & 0x20)) ;
 		*pUART_THR = buff[i];
-		sync();
+		SSYNC();
 		i++;
 	}
 	for (i = 0; i < 0x80000; i++) ;
@@ -141,7 +141,7 @@ int post_key_pressed(void)
 	*pPORTF_FER &= ~PF5;
 	*pPORTFIO_DIR &= ~PF5;
 	*pPORTFIO_INEN |= PF5;
-	sync();
+	SSYNC();
 
 	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
 	for (i = 0; i < KEY_LOOP; i++) {
@@ -303,7 +303,7 @@ int post_init_sdram(int sclk)
 	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
 	     | PSS);
 
-	sync();
+	SSYNC();
 
 	*pEBIU_SDGCTL |= 0x1000000;
 	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
@@ -314,7 +314,7 @@ int post_init_sdram(int sclk)
 
 	/* SDRAM Memory Global Control Register */
 	*pEBIU_SDGCTL = mem_SDGCTL;
-	sync();
+	SSYNC();
 	return mem_SDRRC;
 }
 
diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c
index d9c08ee8e6..c48c3c7c7e 100644
--- a/board/bf537-stamp/stm_m25p64.c
+++ b/board/bf537-stamp/stm_m25p64.c
@@ -4,6 +4,7 @@
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/spi.h>
 
 #if defined(CONFIG_SPI)
 
@@ -142,7 +143,7 @@ void SendSingleCommand(const int iCommand)
 
 	/* sends the actual command to the SPI TX register */
 	*pSPI_TDBR = iCommand;
-	sync();
+	SSYNC();
 
 	/* The SPI status register will be polled to check the SPIF bit */
 	Wait_For_SPIF();
@@ -164,10 +165,10 @@ void SetupSPI(const int spi_setting)
 	*pSPI_FLG = 0xFF02;
 	*pSPI_BAUD = CONFIG_SPI_BAUD;
 	*pSPI_CTL = spi_setting;
-	sync();
+	SSYNC();
 
 	*pSPI_FLG = 0xFD02;
-	sync();
+	SSYNC();
 }
 
 void SPI_OFF(void)
@@ -176,7 +177,7 @@ void SPI_OFF(void)
 	*pSPI_CTL = 0x0400;	/* disable SPI */
 	*pSPI_FLG = 0;
 	*pSPI_BAUD = 0;
-	sync();
+	SSYNC();
 	udelay(CONFIG_CCLK_HZ / 50000000);
 
 }
@@ -234,10 +235,10 @@ char ReadStatusRegister(void)
 	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
 
 	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the instruction has been sent */
 	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
-	sync();
+	SSYNC();
 	Wait_For_SPIF();	/*wait until the data has been sent */
 	status_register = *pSPI_RDBR;	/*read the status register */
 
@@ -300,23 +301,23 @@ ERROR_CODE EraseBlock(int nBlock)
 	 * to point to the start of a sector
 	 */
 	*pSPI_TDBR = SPI_SE;
-	sync();
+	SSYNC();
 	Wait_For_SPIF();
 	/* Send the highest byte of the 24 bit address at first */
 	ShiftValue = (ulSectorOff >> 16);
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the middle byte of the 24 bit address  at second */
 	ShiftValue = (ulSectorOff >> 8);
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the lowest byte of the 24 bit address finally */
 	*pSPI_TDBR = ulSectorOff;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 
@@ -357,33 +358,33 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	/* Send the read command to SPI device */
 	*pSPI_TDBR = SPI_READ;
 #endif
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the highest byte of the 24 bit address at first */
 	ShiftValue = (ulStart >> 16);
 	/* Send the byte to the SPI device */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the middle byte of the 24 bit address  at second */
 	ShiftValue = (ulStart >> 8);
 	/* Send the byte to the SPI device */
 	*pSPI_TDBR = ShiftValue;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/* Send the lowest byte of the 24 bit address finally */
 	*pSPI_TDBR = ulStart;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 
 #ifdef CONFIG_SPI_FLASH_FAST_READ
 	/* Send dummy for FAST_READ */
 	*pSPI_TDBR = 0;
-	sync();
+	SSYNC();
 	/* Wait until the instruction has been sent */
 	Wait_For_SPIF();
 #endif
@@ -392,7 +393,7 @@ ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
 	/* received on the MISO pin. */
 	for (i = 0; i < lCount; i++) {
 		*pSPI_TDBR = 0;
-		sync();
+		SSYNC();
 		while (!(*pSPI_STAT & RXS)) ;
 		*cnData++ = *pSPI_RDBR;
 
@@ -435,22 +436,22 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 		 */
 		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
 	*pSPI_TDBR = SPI_PP;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = (ulStartAddr >> 16);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = (ulStartAddr >> 8);
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	ulWAddr = ulStartAddr;
 	*pSPI_TDBR = ulWAddr;
-	sync();
+	SSYNC();
 	/*wait until the instruction has been sent */
 	Wait_For_SPIF();
 	/*
@@ -460,7 +461,7 @@ ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
 	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
 		iData = *temp;
 		*pSPI_TDBR = iData;
-		sync();
+		SSYNC();
 		/*wait until the instruction has been sent */
 		Wait_For_SPIF();
 		temp++;
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
index 2ff44a7152..d504217a1a 100644
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -65,9 +65,9 @@ int misc_init_r(void)
 	/* Keep PF12 low to be able to drive the USB-LAN Extender */
 	*pFIO0_DIR = 0x0000;
 	*pFIO0_FLAG_C = 0x1000;	/* Clear PF12 */
-	sync();
+	SSYNC();
 	*pFIO0_POLAR = 0x0000;
-	sync();
+	SSYNC();
 
 	return 0;
 }