Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>

67 files changed, 2097 insertions, 556 deletions

diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index 73d69e0388..f67b04b78c 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -8,6 +8,7 @@
 #include <env.h>
 #include <i2c.h>
 #include <init.h>
+#include <mmc.h>
 #include <phy.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
@@ -83,6 +84,7 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+	struct mmc *mmc_dev;
 	bool ddr4, emmc;
 
 	if (env_get("fdtfile"))
@@ -95,7 +97,9 @@ int board_late_init(void)
 	ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
 		& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
 
-	emmc = of_machine_is_compatible("globalscale,espressobin-emmc");
+	/* eMMC is mmc dev num 1 */
+	mmc_dev = find_mmc_device(1);
+	emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
 
 	if (ddr4 && emmc)
 		env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS
index 15660cd17d..55e485faa9 100644
--- a/board/Marvell/mvebu_armada-8k/MAINTAINERS
+++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS
@@ -13,6 +13,7 @@ F:	configs/mvebu_mcbin-88f8040_defconfig
 
 Puzzle-M801 BOARD
 M:	Luka Kovacic <luka.kovacic@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
 S:	Maintained
 F:	configs/mvebu_puzzle-m801-88f8040_defconfig
 F:	arch/arm/dts/armada-8040-puzzle-m801.dts
diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
index b142ee02e6..58a4d253c3 100644
--- a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
+++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
@@ -2,5 +2,6 @@ i.MX8QM ROM 7720 a1 BOARD
 M:	Oliver Graute <oliver.graute@kococonnector.com>
 S:	Maintained
 F:	board/advantech/imx8qm_rom7720_a1/
+F:	arch/arm/dts/imx8qm-rom7720-a1.dts
 F:	include/configs/imx8qm_rom7720.h
 F:	configs/imx8qm_rom7720_a1_4G_defconfig
diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README
deleted file mode 100644
index 585fde440d..0000000000
--- a/board/advantech/imx8qm_rom7720_a1/README
+++ /dev/null
@@ -1,61 +0,0 @@
-U-Boot for the NXP i.MX8QM ROM 7720a1 board
-
-Quick Start
-===========
-
-- Build the ARM Trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Get imx-mkimage
-- Build U-Boot
-- Build imx-mkimage
-- Flash the binary into the SD card
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-
-$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
-$ make PLAT=imx8qm bl31
-
-Get scfw_tcm.bin and ahab-container.img
-==============================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
-$ chmod +x imx-sc-firmware-1.1.bin
-$ ./imx-sc-firmware-1.1.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Or use this to avoid running random scripts from the internet,
-but note that you must agree to the license the script displays:
-
-$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
-$ tar -xf imx-sc-firmware-1.1.tar.bz2
-$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
-
-$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
-$ tar -xf firmware-imx-8.0.tar.bz2
-$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
-
-Build U-Boot
-============
-
-$ export ATF_LOAD_ADDR=0x80000000
-$ export BL33_LOAD_ADDR=0x80020000
-$ make imx8qm_rom7720_a1_4G_defconfig
-$ make u-boot.bin
-$ make flash.bin
-
-Flash the binary into the SD card
-=================================
-
-Burn the flash.bin binary to SD card offset 32KB:
-
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
-
-Boot
-====
-Set Boot switch SW2: 1100.
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index 2ad3dbd56c..cc603c1bc2 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -1,28 +1,4 @@
-if TARGET_ARISTAINETOS2
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
-	default "aristainetos"
-
-config SYS_BOARD_VERSION
-	default 2
-
-endif
-
-if TARGET_ARISTAINETOS2B
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
-	default "aristainetos"
-
-config SYS_BOARD_VERSION
-	default 3
-
-endif
-
-if TARGET_ARISTAINETOS2BCSL
+if TARGET_ARISTAINETOS2C
 
 source "board/aristainetos/common/Kconfig"
 
@@ -30,11 +6,11 @@ config SYS_BOARD
 	default "aristainetos"
 
 config SYS_BOARD_VERSION
-	default 4
+	default 5
 
 endif
 
-if TARGET_ARISTAINETOS2C
+if TARGET_ARISTAINETOS2CCSLB
 
 source "board/aristainetos/common/Kconfig"
 
@@ -42,6 +18,6 @@ config SYS_BOARD
 	default "aristainetos"
 
 config SYS_BOARD_VERSION
-	default 5
+	default 6
 
 endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index b4ca7abb9c..c81bef9cb7 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -3,34 +3,16 @@ M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/aristainetos/
 F:	include/configs/aristainetos2.h
-F:	configs/aristainetos2_defconfig
-F:	configs/aristainetos2b_defconfig
-F:	configs/aristainetos2bcsl_defconfig
 F:	configs/aristainetos2c_defconfig
-F:	arch/arm/dts/imx6qdl-aristainetos2.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2_4.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2c_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+F:	configs/aristainetos2ccslb_defconfig
 F:	arch/arm/dts/imx6dl-aristainetos2c_7.dts
 F:	arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2c.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 14931120f6..07d2e3ec7b 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -27,6 +27,7 @@
 #include <bmp_logo.h>
 #include <dm/root.h>
 #include <env.h>
+#include <env_internal.h>
 #include <i2c_eeprom.h>
 #include <i2c.h>
 #include <micrel.h>
@@ -194,87 +195,6 @@ static void enable_lvds(struct display_info_t const *dev)
 	writel(reg, &iomux->gpr[3]);
 }
 
-static void enable_spi_display(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-	s32 timeout = 100000;
-
-#if defined(CONFIG_VIDEO_BMP_LOGO)
-	rotate_logo(3);  /* portrait display in landscape mode */
-#endif
-
-	reg = readl(&ccm->cs2cdr);
-
-	/* select pll 5 clock */
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	writel(reg, &ccm->cs2cdr);
-
-	/* set PLL5 to 197994996Hz */
-	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
-	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
-	writel(reg, &ccm->analog_pll_video);
-
-	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
-	       &ccm->analog_pll_video_num);
-	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
-	       &ccm->analog_pll_video_denom);
-
-	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
-	writel(reg, &ccm->analog_pll_video);
-
-	while (timeout--)
-		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
-			break;
-	if (timeout < 0)
-		printf("Warning: video pll lock timeout!\n");
-
-	reg = readl(&ccm->analog_pll_video);
-	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
-	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
-	writel(reg, &ccm->analog_pll_video);
-
-	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
-	reg = readl(&ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &ccm->cs2cdr);
-
-	reg = readl(&ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &ccm->cscmr2);
-
-	reg = readl(&ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
-	writel(reg, &ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
-	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
-	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-}
-
 static void setup_display(void)
 {
 	enable_ipu_clock();
@@ -331,25 +251,36 @@ static void setup_board_gpio(void)
 	setup_one_led("led_blue", LEDST_OFF);
 }
 
-#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
-		" rescueReason=%d "
-
 static void aristainetos_run_rescue_command(int reason)
 {
-	char rescue_reason_command[80];
+	char rescue_reason_command[20];
 
-	sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
+	sprintf(rescue_reason_command, "setenv rreason %d", reason);
 	run_command(rescue_reason_command, 0);
 }
 
-static int aristainetos_eeprom(void)
+static int aristainetos_bootmode_settings(void)
 {
+	struct gpio_desc *desc;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int sbmr1 = readl(&psrc->sbmr1);
+	char *my_bootdelay;
+	char bootmode = 0;
+	int ret;
 	struct udevice *dev;
 	int off;
-	int ret;
 	u8 data[0x10];
 	u8 rescue_reason;
 
+	/* jumper controlled reset of the environment */
+	ret = gpio_hog_lookup_name("env_reset", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			printf("\nReset u-boot environment (jumper)\n");
+			run_command("run default_env; saveenv; saveenv", 0);
+		}
+	}
+
 	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 	if (off < 0) {
 		printf("%s: No eeprom0 path offset\n", __func__);
@@ -366,37 +297,26 @@ static int aristainetos_eeprom(void)
 	if (ret)
 		return ret;
 
-	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
+	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
 	if (ret) {
 		printf("%s: Could not read EEPROM\n", __func__);
 		return ret;
 	}
 
-	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
-		rescue_reason = *(uint8_t *)&data[9];
-		memset(&data[3], 0xff, 7);
-		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
-		printf("\nBooting into Rescue System (EEPROM)\n");
-		aristainetos_run_rescue_command(rescue_reason);
-		run_command("run rescue_load_fit rescueboot", 0);
-	} else if (strncmp((char *)data, "DeF", 3) == 0) {
+	/* software controlled reset of the environment (EEPROM magic) */
+	if (strncmp((char *)data, "DeF", 3) == 0) {
 		memset(data, 0xff, 3);
 		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
-		printf("\nClear u-boot environment (set back to defaults)\n");
+		printf("\nReset u-boot environment (EEPROM)\n");
 		run_command("run default_env; saveenv; saveenv", 0);
 	}
 
-	return 0;
-};
-
-static void aristainetos_bootmode_settings(void)
-{
-	struct gpio_desc *desc;
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned int sbmr1 = readl(&psrc->sbmr1);
-	char *my_bootdelay;
-	char bootmode = 0;
-	int ret;
+	if (sbmr1 & 0x40) {
+		env_set("bootmode", "1");
+		printf("SD bootmode jumper set!\n");
+	} else {
+		env_set("bootmode", "0");
+	}
 
 	/*
 	 * Check the boot-source. If booting from NOR Flash,
@@ -420,28 +340,27 @@ static void aristainetos_bootmode_settings(void)
 			env_set("bootdelay", "-2");
 	}
 
-	if (sbmr1 & 0x40) {
-		env_set("bootmode", "1");
-		printf("SD bootmode jumper set!\n");
-	} else {
-		env_set("bootmode", "0");
-	}
-
-	/* read out some jumper values*/
-	ret = gpio_hog_lookup_name("env_reset", &desc);
-	if (!ret) {
-		if (dm_gpio_get_value(desc)) {
-			printf("\nClear env (set back to defaults)\n");
-			run_command("run default_env; saveenv; saveenv", 0);
-		}
-	}
+	/* jumper controlled boot of the rescue system */
 	ret = gpio_hog_lookup_name("boot_rescue", &desc);
 	if (!ret) {
 		if (dm_gpio_get_value(desc)) {
+			printf("\nBooting into Rescue System (jumper)\n");
 			aristainetos_run_rescue_command(16);
 			run_command("run rescue_xload_boot", 0);
 		}
 	}
+
+	/* software controlled boot of the rescue system (EEPROM magic) */
+	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+		rescue_reason = *(uint8_t *)&data[9];
+		memset(&data[3], 0xff, 7);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+		printf("\nBooting into Rescue System (EEPROM)\n");
+		aristainetos_run_rescue_command(rescue_reason);
+		run_command("run rescue_xload_boot", 0);
+	}
+
+	return 0;
 }
 
 #if defined(CONFIG_DM_PMIC_DA9063)
@@ -497,15 +416,15 @@ static int setup_pmic_voltages(void)
 int board_late_init(void)
 {
 	int x, y;
+	int ret;
 
 	led_default_state();
 	splash_get_pos(&x, &y);
 	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 
-	aristainetos_bootmode_settings();
-
-	/* eeprom work */
-	aristainetos_eeprom();
+	ret = aristainetos_bootmode_settings();
+	if (ret)
+		return ret;
 
 	/* set board_type */
 	if (gd->board_type == BOARD_TYPE_4)
@@ -549,97 +468,9 @@ struct display_info_t const displays[] = {
 			.vmode          = FB_VMODE_NONINTERLACED
 		}
 	}
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
-	(CONFIG_SYS_BOARD_VERSION == 3) || \
-	(CONFIG_SYS_BOARD_VERSION == 4) || \
-	(CONFIG_SYS_BOARD_VERSION == 5))
-	, {
-		.bus	= -1,
-		.addr	= 0,
-		.pixfmt	= IPU_PIX_FMT_RGB24,
-		.detect	= NULL,
-		.enable	= enable_spi_display,
-		.mode	= {
-			.name           = "lg4573",
-			.refresh        = 57,
-			.xres           = 480,
-			.yres           = 800,
-			.pixclock       = 37037,
-			.left_margin    = 59,
-			.right_margin   = 10,
-			.upper_margin   = 15,
-			.lower_margin   = 15,
-			.hsync_len      = 10,
-			.vsync_len      = 15,
-			.sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
-					  FB_SYNC_VERT_HIGH_ACT,
-			.vmode          = FB_VMODE_NONINTERLACED
-		}
-	}
-#endif
 };
 size_t display_count = ARRAY_SIZE(displays);
 
-#if defined(CONFIG_MTD_RAW_NAND)
-iomux_v3_cfg_t nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__NAND_CE0_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D0__NAND_DATA00		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D1__NAND_DATA01		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D2__NAND_DATA02		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D3__NAND_DATA03		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D4__NAND_DATA04		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D5__NAND_DATA05		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D6__NAND_DATA06		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D7__NAND_DATA07		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads,
-					 ARRAY_SIZE(nfc_pads));
-
-	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
-	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable ENFC_CLK_ROOT clock */
-	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#else
-static void setup_gpmi_nand(void)
-{
-}
-#endif
-
 int board_init(void)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -648,7 +479,6 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 	setup_board_gpio();
-	setup_gpmi_nand();
 	setup_display();
 
 	/* GPIO_1 for USB_OTG_ID */
@@ -698,3 +528,22 @@ int embedded_dtb_select(void)
 	return 0;
 }
 #endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_SPI_FLASH;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_SPI_FLASH;
+
+	default:
+		return ENVL_UNKNOWN;
+	}
+
+	return ENVL_UNKNOWN;
+}
diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig
index e26de5144d..328243c2f9 100644
--- a/board/aristainetos/common/Kconfig
+++ b/board/aristainetos/common/Kconfig
@@ -2,10 +2,8 @@ config SYS_BOARD_VERSION
 	int "select version of aristainetos board"
 	help
 	  version of aristainetos board version
-	  2 version 2
-	  3 version 2b
-	  4 version 2bcsl
-	  5 version 2c
+	  5 version 2c and 2d
+	  6 version 2c-cslb
 
 config SYS_I2C_MXC_I2C1
 	default y
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 93638d2452..0860bd2312 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -141,4 +141,29 @@ void qixis_write_i2c(unsigned int reg, u8 value);
 
 #define QIXIS_EVDD_BY_SDHC_VS	0x0c
 
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
+defined(CONFIG_TARGET_LX2160ARDB)
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
+#define QIXIS_RCW_SRC_SD		0x08
+#define QIXIS_RCW_SRC_EMMC         0x09
+#define NON_EXTENDED_DUTCFG
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define QIXIS_SDID_MASK			0x07
+#define QIXIS_ESDHC_NO_ADAPTER		0x7
+#endif
+
 #endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 728245d81c..33ae4c15ba 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -175,9 +175,11 @@ static int read_eeprom(void)
 	struct udevice *dev;
 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
-				      CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 #else
-	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 #endif
 	if (!ret)
 		ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 9c51f50260..2617f61520 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -484,10 +485,10 @@ int adjust_vdd(ulong vdd_override)
 	u8 vid;
 #endif
 	int vdd_target, vdd_current, vdd_last;
-	int ret, i2caddress;
+	int ret, i2caddress = 0;
 	unsigned long vdd_string_override;
 	char *vdd_string;
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	static const u16 vdd[32] = {
 		8250,
 		7875,
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index 65b348ee42..5bbaecace4 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __VID_H_
@@ -37,6 +38,35 @@
  */
 #define EN_WRITE_ALL_CMD (0)
 
+#ifdef CONFIG_TARGET_LX2160ARDB
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			855
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			925
+#endif
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
+defined(CONFIG_TARGET_LX2160ARDB)
+/* PM Bus commands code for LTC3882*/
+#define PWM_CHANNEL0                    0x0
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define I2C_VOL_MONITOR_ADDR            0x63
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+#endif
+
 int adjust_vdd(ulong vdd_override);
 
 #endif  /* __VID_H_ */
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 8112c12568..6500c2fcf6 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "emi1_rgmii");
 			break;
 		default:
@@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis)
 				miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * If DTSEC4 is RGMII, then it's routed via via EC1 to
 			 * the first on-board RGMII port.  If DTSEC5 is RGMII,
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 650013bb6f..df5a69bcba 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis)
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
@@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis)
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index 35daa1e80f..de7b692f3f 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis)
 			miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis)
 
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 55b414e168..4ac69d7117 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -16,6 +16,10 @@ config SYS_LS_PFE_FW_ADDR
 	hex "Flash address of PFE firmware"
 	default 0x40a00000
 
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x40000
+
 config SYS_LS_PPA_FW_ADDR
 	hex "PPA Firmware Addr"
 	default 0x40400000
@@ -65,6 +69,10 @@ config SYS_LS_PFE_FW_ADDR
 	hex "Flash address of PFE firmware"
 	default 0x40020000
 
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x40000
+
 config SYS_LS_PPA_FW_ADDR
 	hex "PPA Firmware Addr"
 	default 0x40060000
@@ -77,6 +85,9 @@ config SYS_LS_PFE_ESBC_ADDR
 	hex "PFE Firmware HDR Addr"
 	default 0x401f8000
 
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
 endif
 
 if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index 8844557aae..59b1a87665 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -20,6 +20,14 @@ if CHAIN_OF_TRUST
 config SYS_LS_PPA_ESBC_ADDR
 	hex "PPA Firmware HDR Addr"
 	default 0x40680000
+
+config SYS_LS_PFE_ESBC_ADDR
+	hex "PFE Firmware HDR Addr"
+	default 0x40700000
+
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
 endif
 
 if FSL_PFE
@@ -39,9 +47,9 @@ config SYS_LS_PFE_FW_ADDR
 	hex "Flash address of PFE firmware"
 	default 0x40a00000
 
-config SYS_LS_PFE_ESBC_ADDR
-	hex "PFE Firmware HDR Addr"
-	default 0x40700000
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
 
 config DDR_PFE_PHYS_BASEADDR
 	hex "PFE DDR physical base address"
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index 5a2fa91f6b..c4acea3ae2 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -20,6 +20,14 @@ if CHAIN_OF_TRUST
 config SYS_LS_PPA_ESBC_ADDR
 	hex "PPA Firmware HDR Addr"
 	default 0x40680000
+
+config SYS_LS_PFE_ESBC_ADDR
+	hex "PFE Firmware HDR Addr"
+	default 0x40640000
+
+config SYS_LS_PFE_ESBC_LENGTH
+	hex "length of PFE Firmware HDR"
+	default 0xc00
 endif
 
 if FSL_PFE
@@ -33,9 +41,9 @@ config SYS_LS_PFE_FW_ADDR
 	hex "Flash address of PFE firmware"
 	default 0x40a00000
 
-config SYS_LS_PFE_ESBC_ADDR
-	hex "PFE Firmware HDR Addr"
-	default 0x40640000
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
 
 config DDR_PFE_PHYS_BASEADDR
 	hex "PFE DDR physical base address"
@@ -89,6 +97,10 @@ config SYS_LS_PFE_FW_ADDR
 	hex "Flash address of PFE firmware"
 	default 0x40a00000
 
+config SYS_LS_PFE_FW_LENGTH
+	hex "length of PFE firmware"
+	default 0x300000
+
 config DDR_PFE_PHYS_BASEADDR
 	hex "PFE DDR physical base address"
 	default 0x03800000
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 95412df1d7..c3efe8a0be 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -479,6 +479,8 @@ int board_eth_init(struct bd_info *bis)
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4)
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 8f5f95e396..33db552adb 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -409,6 +409,8 @@ int board_eth_init(struct bd_info *bis)
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4)
diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig
index 122a385100..7556f7dd21 100644
--- a/board/freescale/lx2160a/Kconfig
+++ b/board/freescale/lx2160a/Kconfig
@@ -32,3 +32,19 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 endif
 
+if TARGET_LX2162AQDS
+
+config SYS_BOARD
+	default "lx2160a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "lx2162aqds"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS
index 9fe79c0ef7..c627417cf7 100644
--- a/board/freescale/lx2160a/MAINTAINERS
+++ b/board/freescale/lx2160a/MAINTAINERS
@@ -1,4 +1,5 @@
 LX2160ARDB BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
 M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/lx2160a/
@@ -14,6 +15,7 @@ S:	Maintained
 F:	configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
 
 LX2160AQDS BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
 M:	Pankaj Bansal <pankaj.bansal@nxp.com>
 S:	Maintained
 F:	board/freescale/lx2160a/eth_lx2160aqds.h
@@ -25,3 +27,27 @@ LX2160AQDS_SECURE_BOOT BOARD
 M:	Udit Agarwal <udit.agarwal@nxp.com>
 S:	Maintained
 F:	configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+
+LX2162AQDS BOARD
+M:	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
+S:	Maintained
+F:	board/freescale/lx2160a/eth_lx2162aqds.h
+F:	include/configs/lx2162aqds.h
+F:	configs/lx2162aqds_tfa_defconfig
+F:	arch/arm/dts/fsl-lx2162a-qds.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-17-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-18-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-20-x.dts
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
+F:	arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
+
+LX2162AQDS_SECURE_BOOT BOARD
+M:	Manish Tomar <Manish.Tomar@nxp.com>
+S:	Maintained
+F:	configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+
+LX2162AQDS_VERIFIED_BOOT BOARD
+M:	Manish Tomar <Manish.Tomar@nxp.com>
+S:	Maintained
+F:	configs/lx2162aqds_tfa_verified_boot_defconfig
diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile
index d1a621b682..c9561bfade 100644
--- a/board/freescale/lx2160a/Makefile
+++ b/board/freescale/lx2160a/Makefile
@@ -8,3 +8,4 @@ obj-y += lx2160a.o
 obj-y += ddr.o
 obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
 obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
+obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README
index 62fb9eab15..7bca98dd3d 100644
--- a/board/freescale/lx2160a/README
+++ b/board/freescale/lx2160a/README
@@ -195,3 +195,135 @@ SERDES3	|CARDS
 	|Connect I/O cable to IO_SLOT6(J125)
 -------------------------------------------------------------------------
 
+LX2162A SoC Overview
+--------------------------------------
+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+LX2162AQDS board Overview
+----------------------
+DDR Memory
+	One ports of 72-bits (8-bits ECC) DDR4.
+	Each port supports four chip-selects and two DIMM
+	connectors. Data rate upto 2.9 GT/s.
+
+SERDES ports
+	Two serdes controllers (12 lanes)
+	Serdes1: Supports two USXGMII connectors, each connected through
+	Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
+	IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
+	CS4223 phy.
+
+	Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector,
+	four SATA 3.0 connectors
+
+eSDHC
+	eSDHC1: Supports a SD connector for connecting SD cards
+	eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
+
+Octal SPI (XSPI)
+	Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
+	for off-board emulation
+
+I2C	All system devices on I2C1 multiplexed using PCA9547 multiplexer
+	Serial Ports
+
+USB 3.0
+	One high speed USB 3.0 ports. First USB 3.0 port configured as Host
+	with Type-A connector, second USB 3.0 port configured as OTG with
+	micro-AB connector
+
+Serial Ports	Two UART ports
+Ethernet	Two RGMII interfaces
+Debug		ARM JTAG support
+
+Booting Options
+---------------
+a) Flexspi boot
+b) SD boot
+c) eMMC boot
+
+Memory map for Flexspi flash
+----------------------------
+Image							Flash Offset
+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl)			0x00000000
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00100000
+Boot firmware Environment				0x00500000
+DDR PHY Firmware (fip_ddr_all.bin)			0x00800000
+DPAA2 MC Firmware					0x00A00000
+DPAA2 DPL						0x00D00000
+DPAA2 DPC						0x00E00000
+Kernel.itb						0x01000000
+
+Memory map for sd/eMMC card
+----------------------------
+Image							SD/eMMC card Offset
+bl2_sd.pbl (RCW+PBI+bl2.pbl)				0x00008
+fip.bin (bl31 + bl33(u-boot) +
+	 header for Secure-boot(secure-boot only))	0x00800
+Boot firmware Environment				0x02800
+DDR PHY Firmware (fip_ddr_all.bin)			0x04000
+DPAA2 MC Firmware					0x05000
+DPAA2 DPL						0x06800
+DPAA2 DPC						0x07000
+Kernel.itb						0x08000
+
+Various Mezzanine cards and their connection for different SERDES protocols is
+as below:
+
+SERDES1	|CARDS
+-----------------------------------------------------------------------
+1	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M11-USXGMII (29828)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+15	|Mezzanine:X-M8-50G (29734)
+	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+17	|Mezzanine:X-M13-25G  (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect I/O cable to IO_SLOT1(J110)
+------------------------------------------------------------------------
+18	|Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+	|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
+------------------------------------------------------------------------
+20	|Mezzanine:X-M7-40G (29738)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+	|Connect  I/O cable to IO_SLOT1(J108)
+------------------------------------------------------------------------
+
+
+SERDES2	|CARDS
+-----------------------------------------------------------------------
+2	|Mezzanine:X-M6-PCIE-X8 (29737) *
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT3(J116)
+------------------------------------------------------------------------
+3	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+5	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT3(J116)
+	|Mezzanine:X-M5-SATA (29687)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+11	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+	|Connect I/O cable to IO_SLOT7(J127)
+	|Mezzanine:X-M4-PCIE-SGMII (29733)
+	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+	|Connect I/O cable to IO_SLOT8(J131)
+------------------------------------------------------------------------
diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c
index b448883ee1..b3125b7748 100644
--- a/board/freescale/lx2160a/eth_lx2160ardb.c
+++ b/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  *
  */
 
@@ -19,6 +19,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
+#include "lx2160a.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c
new file mode 100644
index 0000000000..4683f674f0
--- /dev/null
+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -0,0 +1,974 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <log.h>
+#include <net.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <linux/libfdt.h>
+
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_ETH
+#define EMI_NONE	0
+#define EMI1		1 /* Mdio Bus 1 */
+#define EMI2		2 /* Mdio Bus 2 */
+
+#if defined(CONFIG_FSL_MC_ENET)
+enum io_slot {
+	IO_SLOT_NONE = 0,
+	IO_SLOT_1,
+	IO_SLOT_2,
+	IO_SLOT_3,
+	IO_SLOT_4,
+	IO_SLOT_5,
+	IO_SLOT_6,
+	IO_SLOT_7,
+	IO_SLOT_8,
+	EMI1_RGMII1,
+	EMI1_RGMII2,
+	IO_SLOT_MAX
+};
+
+struct lx2162a_qds_mdio {
+	enum io_slot ioslot : 4;
+	u8 realbusnum : 4;
+	struct mii_dev *realbus;
+};
+
+/* structure explaining the phy configuration on 8 lanes of a serdes*/
+struct serdes_phy_config {
+	u8 serdes; /* serdes protocol */
+	struct phy_config {
+		u8 dpmacid;
+		/* -1 terminated array */
+		int phy_address[WRIOP_MAX_PHY_NUM + 1];
+		u8 mdio_bus;
+		enum io_slot ioslot;
+	} phy_config[SRDS_MAX_LANES];
+};
+
+/* Table defining the phy configuration on 8 lanes of a serdes.
+ * Various assumptions have been made while defining this table.
+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
+ * And also that this card is connected to IO Slot 1 (could have been connected
+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
+ * used in serdes1 protocol 19 (could have selected MDIO 2)
+ * To override these settings "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ * This table has limited serdes protocol entries. It can be expanded as per
+ * requirement.
+ */
+/*****************************************************************
+ *|   SERDES_1 PROTOCOL   |      IO_SLOT         |       CARD     |
+ ******************************************************************
+ *|      2                |      IO_SLOT_1       |  M4-PCIE-SGMII |
+ *|      3                |      IO_SLOT_1       |  M11-USXGMII   |
+ *|      15               |      IO_SLOT_1       |  M13-25G       |
+ *|      17               |      IO_SLOT_1       |  M13-25G       |
+ *|      18               |      IO_SLOT_1       |  M11-USXGMII   |
+ *|                       |      IO_SLOT_6       |  M13-25G       |
+ *|      20               |      IO_SLOT_1       |  M7-40G        |
+ *****************************************************************
+ */
+static const struct serdes_phy_config serdes1_phy_config[] = {
+	{1, {} },
+	{2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	     EMI1, IO_SLOT_1} } },
+	{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+	     EMI1, IO_SLOT_1},
+	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+	     EMI1, IO_SLOT_1} } },
+	{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	       EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1} } },
+	{18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_1},
+	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6},
+	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+	      EMI1, IO_SLOT_6} } },
+	{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
+	       EMI1, IO_SLOT_1} } }
+};
+
+/*****************************************************************
+ *|   SERDES_2 PROTOCOL   |      IO_SLOT         |       CARD     |
+ ******************************************************************
+ *|      2                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      3                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      5                |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|      10               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      11               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ *|      12               |      IO_SLOT_7       |  M4-PCIE-SGMII |
+ *|                       |      IO_SLOT_8       |  M4-PCIE-SGMII |
+ ******************************************************************
+ */
+static const struct serdes_phy_config serdes2_phy_config[] = {
+	{2, {} },
+	{3, {} },
+	{5, {} },
+	{10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7} } },
+	{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8},
+	     {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_8} } },
+	{12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+	       EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7},
+	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+	      EMI1, IO_SLOT_7} } }
+};
+
+static inline
+const struct phy_config *get_phy_config(u8 serdes,
+					const struct serdes_phy_config *table,
+					u8 table_size)
+{
+	int i;
+
+	for (i = 0; i < table_size; i++) {
+		if (table[i].serdes == serdes)
+			return table[i].phy_config;
+	}
+
+	return NULL;
+}
+
+/* BRDCFG4 controls EMI routing for the board.
+ * Bits    Function
+ * 7-6     EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
+ * EMI1    00= On-board PHY #1
+ *         01= On-board PHY #2
+ *         10= (reserved)
+ *         11= Slots 1..8 multiplexer and translator.
+ * 5-3     EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
+ * EMI1X   000= Slot #1
+ *         001= Slot #2
+ *         010= Slot #3
+ *         011= Slot #4
+ *         100= Slot #5
+ *         101= Slot #6
+ *         110= Slot #7
+ *         111= Slot #8
+ * 2-0     EMI Interface #2 Routing (CFG_MUX_EMI2):
+ * EMI2    000= Slot #1 (secondary EMI)
+ *         001= Slot #2 (secondary EMI)
+ *         010= Slot #3 (secondary EMI)
+ *         011= Slot #4 (secondary EMI)
+ *         100= Slot #5 (secondary EMI)
+ *         101= Slot #6 (secondary EMI)
+ *         110= Slot #7 (secondary EMI)
+ *         111= Slot #8 (secondary EMI)
+ */
+static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
+{
+	switch (realbusnum) {
+	case EMI1:
+		switch (ioslot) {
+		case EMI1_RGMII1:
+			return 0;
+		case EMI1_RGMII2:
+			return 0x40;
+		default:
+			return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
+		}
+		break;
+	case EMI2:
+		return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
+	default:
+		return -1;
+	}
+}
+
+static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
+{
+	u8 brdcfg4, mux_val, reg;
+
+	brdcfg4 = QIXIS_READ(brdcfg[4]);
+	reg = brdcfg4;
+	mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+
+	switch (priv->realbusnum) {
+	case EMI1:
+		brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	case EMI2:
+		brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
+		brdcfg4 |= mux_val;
+		break;
+	}
+
+	if (brdcfg4 ^ reg)
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
+				 int devad, int regnum)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	lx2162a_qds_mux_mdio(priv);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				  int regnum, u16 value)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	lx2162a_qds_mux_mdio(priv);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct lx2162a_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
+{
+	struct lx2162a_qds_mdio *pmdio;
+	struct mii_dev *bus;
+	/*should be within MDIO_NAME_LEN*/
+	char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
+
+	if (realbusnum == EMI2) {
+		if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else if (realbusnum == EMI1) {
+		if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
+			printf("invalid ioslot %d\n", ioslot);
+			return NULL;
+		}
+	} else {
+		printf("not supported real mdio bus %d\n", realbusnum);
+		return NULL;
+	}
+
+	if (ioslot == EMI1_RGMII1)
+		strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
+	else if (ioslot == EMI1_RGMII2)
+		strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
+	else
+		sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
+			realbusnum, ioslot);
+	bus = miiphy_get_dev_by_name(dummy_mdio_name);
+
+	if (bus)
+		return bus;
+
+	bus = mdio_alloc();
+	if (!bus) {
+		printf("Failed to allocate %s bus\n", dummy_mdio_name);
+		return NULL;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate %s private data\n", dummy_mdio_name);
+		free(bus);
+		return NULL;
+	}
+
+	switch (realbusnum) {
+	case EMI1:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+		break;
+	case EMI2:
+		pmdio->realbus =
+		  miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+		break;
+	}
+
+	if (!pmdio->realbus) {
+		printf("No real mdio bus num %d found\n", realbusnum);
+		free(bus);
+		free(pmdio);
+		return NULL;
+	}
+
+	pmdio->realbusnum = realbusnum;
+	pmdio->ioslot = ioslot;
+	bus->read = lx2162a_qds_mdio_read;
+	bus->write = lx2162a_qds_mdio_write;
+	bus->reset = lx2162a_qds_mdio_reset;
+	strcpy(bus->name, dummy_mdio_name);
+	bus->priv = pmdio;
+
+	if (!mdio_register(bus))
+		return bus;
+
+	printf("No bus with name %s\n", dummy_mdio_name);
+	free(bus);
+	free(pmdio);
+	return NULL;
+}
+
+static inline void do_phy_config(const struct phy_config *phy_config)
+{
+	struct mii_dev *bus;
+	int i, phy_num, phy_address;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (!phy_config[i].dpmacid)
+			continue;
+
+		for (phy_num = 0;
+		     phy_num < ARRAY_SIZE(phy_config[i].phy_address);
+		     phy_num++) {
+			phy_address = phy_config[i].phy_address[phy_num];
+			if (phy_address == -1)
+				break;
+			wriop_set_phy_address(phy_config[i].dpmacid,
+					      phy_num, phy_address);
+		}
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
+					    phy_config[i].ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       phy_config[i].mdio_bus,
+			       phy_config[i].ioslot);
+		else
+			wriop_set_mdio(phy_config[i].dpmacid, bus);
+	}
+}
+
+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
+				   char *env_dpmac)
+{
+	const char *ret;
+	size_t len;
+	u8 realbusnum, ioslot;
+	struct mii_dev *bus;
+	int phy_num;
+	char *phystr = "phy00";
+
+	/*search phy in dpmac arg*/
+	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+		sprintf(phystr, "phy%d", phy_num + 1);
+		ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
+		if (!ret) {
+			/*look for phy instead of phy1*/
+			if (!phy_num)
+				ret = hwconfig_subarg_f(arg_dpmacid, "phy",
+							&len, env_dpmac);
+			if (!ret)
+				continue;
+		}
+
+		if (len != 4 || strncmp(ret, "0x", 2))
+			printf("invalid phy format in %s variable.\n"
+			       "specify phy%d for %s in hex format e.g. 0x12\n",
+			       env_dpmac, phy_num + 1, arg_dpmacid);
+		else
+			wriop_set_phy_address(dpmac, phy_num,
+					      simple_strtoul(ret, NULL, 16));
+	}
+
+	/*search mdio in dpmac arg*/
+	ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
+	if (ret)
+		realbusnum = *ret - '0';
+	else
+		realbusnum = EMI_NONE;
+
+	if (realbusnum) {
+		/*search io in dpmac arg*/
+		ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
+		if (ret)
+			ioslot = *ret - '0';
+		else
+			ioslot = IO_SLOT_NONE;
+		/*Register the muxing front-ends to the MDIO buses*/
+		bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
+		if (!bus)
+			printf("could not get bus for mdio %d ioslot %d\n",
+			       realbusnum, ioslot);
+		else
+			wriop_set_mdio(dpmac, bus);
+	}
+}
+
+#endif
+#endif /* !CONFIG_DM_ETH */
+
+int board_eth_init(struct bd_info *bis)
+{
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+	struct memac_mdio_info mdio_info;
+	struct memac_mdio_controller *regs;
+	int i;
+	const char *ret;
+	char *env_dpmac;
+	char dpmacid[] = "dpmac00", srds[] = "00_00_00";
+	size_t len;
+	struct mii_dev *bus;
+	const struct phy_config *phy_config;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1, srds_s2;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = in_le32(&gur->rcwsr[28]) &
+		  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	sprintf(srds, "%d_%d", srds_s1, srds_s2);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/*Register the EMI 1*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = regs;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/*Register the EMI 2*/
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	/* "dpmac" environment variable can be used after
+	 * defining "dpmac_override" in hwconfig environment variable.
+	 */
+	if (hwconfig("dpmac_override")) {
+		env_dpmac = env_get("dpmac");
+		if (env_dpmac) {
+			ret = hwconfig_arg_f("srds", &len, env_dpmac);
+			if (ret) {
+				if (strncmp(ret, srds, strlen(srds))) {
+					printf("SERDES configuration changed.\n"
+					       "previous: %.*s, current: %s.\n"
+					       "update dpmac variable.\n",
+					       (int)len, ret, srds);
+				}
+			} else {
+				printf("SERDES configuration not found.\n"
+				       "Please add srds:%s in dpmac variable\n",
+				       srds);
+			}
+
+			for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+				/* Look for dpmac1 to dpmac24(current max) arg
+				 * in dpmac environment variable
+				 */
+				sprintf(dpmacid, "dpmac%d", i);
+				ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
+				if (ret)
+					do_dpmac_config(i, dpmacid, env_dpmac);
+			}
+		} else {
+			printf("Warning: environment dpmac not found.\n"
+			       "DPAA network interfaces may not work\n");
+		}
+	} else {
+		/*Look for phy config for serdes1 in phy config table*/
+		phy_config = get_phy_config(srds_s1, serdes1_phy_config,
+					    ARRAY_SIZE(serdes1_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
+			       __func__, srds_s1);
+		} else {
+			do_phy_config(phy_config);
+		}
+		phy_config = get_phy_config(srds_s2, serdes2_phy_config,
+					    ARRAY_SIZE(serdes2_phy_config));
+		if (!phy_config) {
+			printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
+			       __func__, srds_s2);
+		} else {
+			do_phy_config(phy_config);
+		}
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
+		bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
+		if (!bus)
+			printf("could not get bus for RGMII1\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC17, bus);
+	}
+
+	if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
+		wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
+		bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
+		if (!bus)
+			printf("could not get bus for RGMII2\n");
+		else
+			wriop_set_mdio(WRIOP1_DPMAC18, bus);
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_PHY_AQUANTIA
+	/*
+	 * Export functions to be used by AQ firmware
+	 * upload application
+	 */
+	gd->jt->strcpy = strcpy;
+	gd->jt->mdelay = mdelay;
+	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+	gd->jt->phy_find_by_mask = phy_find_by_mask;
+	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+
+#ifdef CONFIG_DM_ETH
+	return 0;
+#else
+	return pci_eth_init(bis);
+#endif
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifndef CONFIG_DM_ETH
+#if defined(CONFIG_FSL_MC_ENET)
+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
+{
+	int offset;
+	int ret;
+	char dpmac_str[] = "dpmacs@00";
+	const char *phy_string;
+
+	offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+	if (offset < 0) {
+		printf("dpmacs node not found in device tree\n");
+		return offset;
+	}
+
+	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+	debug("dpmac_str = %s\n", dpmac_str);
+
+	offset = fdt_subnode_offset(fdt, offset, dpmac_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", dpmac_str);
+		return offset;
+	}
+
+	phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+	if (is_backplane_mode(phy_string)) {
+		/* Backplane KR mode: skip fixups */
+		printf("Interface %d in backplane KR mode\n", dpmac_id);
+		return 0;
+	}
+
+	ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
+	ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
+				 phy_string);
+	if (ret)
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+	return ret;
+}
+
+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
+{
+	char mdio_ioslot_str[] = "mdio@00";
+	struct lx2162a_qds_mdio *priv;
+	u64 reg;
+	u32 phandle;
+	int offset, mux_val;
+
+	/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
+	if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
+		    strlen("LX2162A_QDS_MDIO")))
+		return -1;
+
+	/*Get the real MDIO bus num and ioslot info from bus's priv data*/
+	priv = mii_dev->priv;
+
+	debug("real_bus_num = %d, ioslot = %d\n",
+	      priv->realbusnum, priv->ioslot);
+
+	if (priv->realbusnum == EMI1)
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	else
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+
+	offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
+	if (offset < 0) {
+		printf("mdio@%llx node not found in device tree\n", reg);
+		return offset;
+	}
+
+	phandle = fdt_get_phandle(fdt, offset);
+	phandle = cpu_to_fdt32(phandle);
+	offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
+					       &phandle, 4);
+	if (offset < 0) {
+		printf("mdio-mux-%d node not found in device tree\n",
+		       priv->realbusnum == EMI1 ? 1 : 2);
+		return offset;
+	}
+
+	mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+	if (priv->realbusnum == EMI1)
+		mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
+	else
+		mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
+	sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
+
+	offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
+	if (offset < 0) {
+		printf("%s node not found in device tree\n", mdio_ioslot_str);
+		return offset;
+	}
+
+	return offset;
+}
+
+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
+			struct phy_device *phy_dev, int phandle)
+{
+	char phy_node_name[] = "ethernet-phy@00";
+	char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
+	int ret;
+
+	sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
+	debug("phy_node_name = %s\n", phy_node_name);
+
+	*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
+	if (*subnodeoffset <= 0) {
+		printf("Could not add subnode %s inside node %s err = %s\n",
+		       phy_node_name, fdt_get_name(fdt, offset, NULL),
+		       fdt_strerror(*subnodeoffset));
+		return *subnodeoffset;
+	}
+
+	sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
+		phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
+	debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
+
+	ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
+				 phy_id_compatible_str);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	if (phy_dev->is_c45) {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c45");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	} else {
+		ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+					    "ethernet-phy-ieee802.3-c22");
+		if (ret) {
+			printf("%d@%s %d\n", __LINE__, __func__, ret);
+			goto out;
+		}
+	}
+
+	ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+	ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
+	if (ret) {
+		printf("%d@%s %d\n", __LINE__, __func__, ret);
+		goto out;
+	}
+
+out:
+	if (ret)
+		fdt_del_node(fdt, *subnodeoffset);
+
+	return ret;
+}
+
+#define is_rgmii(dpmac_id) \
+	wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
+
+int fdt_fixup_board_phy(void *fdt)
+{
+	int fpga_offset, offset, subnodeoffset;
+	struct mii_dev *mii_dev;
+	struct list_head *mii_devs, *entry;
+	int ret, dpmac_id, phandle, i;
+	struct phy_device *phy_dev;
+	char ethname[ETH_NAME_LEN];
+	phy_interface_t	phy_iface;
+
+	ret = 0;
+	/* we know FPGA is connected to i2c0, therefore search path directly,
+	 * instead of compatible property, as it saves time
+	 */
+	fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
+
+	if (fpga_offset < 0)
+		fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
+
+	if (fpga_offset < 0) {
+		printf("i2c@2000000/fpga node not found in device tree\n");
+		return fpga_offset;
+	}
+
+	phandle = fdt_alloc_phandle(fdt);
+	mii_devs = mdio_get_list_head();
+
+	list_for_each(entry, mii_devs) {
+		mii_dev = list_entry(entry, struct mii_dev, link);
+		debug("mii_dev name : %s\n", mii_dev->name);
+		offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
+		if (offset < 0)
+			continue;
+
+		// Look for phy devices attached to MDIO bus muxing front end
+		// and create their entries with compatible being the device id
+		for (i = 0; i < PHY_MAX_ADDR; i++) {
+			phy_dev = mii_dev->phymap[i];
+			if (!phy_dev)
+				continue;
+
+			// TODO: use sscanf instead of loop
+			dpmac_id = WRIOP1_DPMAC1;
+			while (dpmac_id < NUM_WRIOP_PORTS) {
+				phy_iface = wriop_get_enet_if(dpmac_id);
+				snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
+					 dpmac_id,
+					 phy_string_for_interface(phy_iface));
+				if (strcmp(ethname, phy_dev->dev->name) == 0)
+					break;
+				dpmac_id++;
+			}
+			if (dpmac_id == NUM_WRIOP_PORTS)
+				continue;
+
+			if ((dpmac_id == 17 || dpmac_id == 18) &&
+			    is_rgmii(dpmac_id))
+				continue;
+
+			ret = fdt_create_phy_node(fdt, offset, i,
+						  &subnodeoffset,
+						  phy_dev, phandle);
+			if (ret)
+				break;
+
+			ret = fdt_fixup_dpmac_phy_handle(fdt,
+							 dpmac_id, phandle);
+			if (ret) {
+				fdt_del_node(fdt, subnodeoffset);
+				break;
+			}
+			/* calculate offset again as new node addition may have
+			 * changed offset;
+			 */
+			offset = fdt_get_ioslot_offset(fdt, mii_dev,
+						       fpga_offset);
+			phandle++;
+		}
+
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+#endif // CONFIG_FSL_MC_ENET
+#endif
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+	u8 serdes_block;
+	u32 serdes_protocol;
+	bool dts_needed;
+} supported_protocols[] = {
+	/* Serdes block #1 */
+	{1, 2, true},
+	{1, 3, true},
+	{1, 15, true},
+	{1, 17, true},
+	{1, 18, true},
+	{1, 20, true},
+
+	/* Serdes block #2 */
+	{2, 2, false},
+	{2, 3, false},
+	{2, 5, false},
+	{2, 10, false},
+	{2, 11, true},
+	{2, 12, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol)
+			return true;
+	}
+
+	return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+	struct serdes_configuration serdes_conf;
+	int i;
+
+	for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+		serdes_conf = supported_protocols[i];
+		if (serdes_conf.serdes_block == serdes_block &&
+		    serdes_conf.serdes_protocol == protocol) {
+			if (serdes_conf.dts_needed == true)
+				sprintf(str, "%u", protocol);
+			else
+				sprintf(str, "x");
+			return;
+		}
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcw_status = in_le32(&gur->rcwsr[28]);
+	char srds_s1_str[2], srds_s2_str[2];
+	u32 srds_s1, srds_s2;
+	char expected_dts[100];
+
+	srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+	/* Check for supported protocols. The default DTS will be used
+	 * in this case
+	 */
+	if (!protocol_supported(1, srds_s1) ||
+	    !protocol_supported(2, srds_s2))
+		return -1;
+
+	get_str_protocol(1, srds_s1, srds_s1_str);
+	get_str_protocol(2, srds_s2, srds_s2_str);
+
+	sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
+		srds_s1_str, srds_s2_str);
+
+	if (!strcmp(name, expected_dts))
+		return 0;
+
+	return -1;
+}
+#endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 8d0115eace..99417aa40d 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -32,12 +32,13 @@
 #include "../common/vid.h"
 #include <fsl_immap.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include "lx2160a.h"
 
 #ifdef CONFIG_EMC2305
 #include "../common/emc2305.h"
 #endif
 
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 #define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
 #define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)	((reg & 0xcf) | value)
@@ -47,7 +48,7 @@
 #define SDHC1_BASE_PMUX_DSPI			2
 #define SDHC2_BASE_PMUX_DSPI			2
 #define IIC5_PMUX_SPI3				3
-#endif /* CONFIG_TARGET_LX2160AQDS */
+#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -191,7 +192,7 @@ int board_fix_fdt(void *fdt)
 }
 #endif
 
-#if defined(CONFIG_TARGET_LX2160AQDS)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 void esdhc_dspi_status_fixup(void *blob)
 {
 	const char esdhc0_path[] = "/soc/esdhc@2140000";
@@ -259,7 +260,7 @@ void esdhc_dspi_status_fixup(void *blob)
 
 int esdhc_status_fixup(void *blob, const char *compat)
 {
-#if defined(CONFIG_TARGET_LX2160AQDS)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	/* Enable esdhc and dspi DT nodes based on RCW fields */
 	esdhc_dspi_status_fixup(blob);
 #else
@@ -297,7 +298,7 @@ int checkboard(void)
 	enum boot_src src = get_boot_src();
 	char buf[64];
 	u8 sw;
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	int clock;
 	static const char *const freq[] = {"100", "125", "156.25",
 					   "161.13", "322.26", "", "", "",
@@ -306,7 +307,7 @@ int checkboard(void)
 #endif
 
 	cpu_name(buf);
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	printf("Board: %s-QDS, ", buf);
 #else
 	printf("Board: %s-RDB, ", buf);
@@ -339,7 +340,13 @@ int checkboard(void)
 			break;
 		}
 	}
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160ARDB)
+	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
+	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+	puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+#else
 	printf("FPGA: v%d (%s), build %d",
 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
 	       (int)qixis_read_minor());
@@ -350,31 +357,27 @@ int checkboard(void)
 	sw = QIXIS_READ(brdcfg[2]);
 	clock = sw >> 4;
 	printf("Clock1 = %sMHz ", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
 	clock = sw & 0x0f;
 	printf("Clock2 = %sMHz", freq[clock]);
-
+#endif
 	sw = QIXIS_READ(brdcfg[3]);
 	puts("\nSERDES2 Reference : ");
 	clock = sw >> 4;
 	printf("Clock1 = %sMHz ", freq[clock]);
 	clock = sw & 0x0f;
-	printf("Clock2 = %sMHz", freq[clock]);
-
+	printf("Clock2 = %sMHz\n", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
 	sw = QIXIS_READ(brdcfg[12]);
-	puts("\nSERDES3 Reference : ");
+	puts("SERDES3 Reference : ");
 	clock = sw >> 4;
 	printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
-#else
-	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
-	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
-	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
-	puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+#endif
 #endif
 	return 0;
 }
 
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 /*
  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
  */
@@ -562,7 +565,7 @@ int config_board_mux(void)
 
 unsigned long get_board_sys_clk(void)
 {
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x03) {
@@ -581,7 +584,7 @@ unsigned long get_board_sys_clk(void)
 
 unsigned long get_board_ddr_clk(void)
 {
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch ((ddrclk_conf & 0x30) >> 4) {
diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h
new file mode 100644
index 0000000000..52b020765d
--- /dev/null
+++ b/board/freescale/lx2160a/lx2160a.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __LX2160_H
+#define __LX2160_H
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+/* SYSCLK */
+#define QIXIS_SYSCLK_100		0x0
+#define QIXIS_SYSCLK_125		0x1
+#define QIXIS_SYSCLK_133		0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100		0x0
+#define QIXIS_DDRCLK_125		0x1
+#define QIXIS_DDRCLK_133		0x2
+
+#define BRDCFG4_EMI1SEL_MASK		0xF8
+#define BRDCFG4_EMI1SEL_SHIFT		3
+#define BRDCFG4_EMI2SEL_MASK		0x07
+#define BRDCFG4_EMI2SEL_SHIFT		0
+#endif
+
+#define QIXIS_XMAP_SHIFT		5
+
+/* RTC */
+#define I2C_MUX_CH_RTC			0xB
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define AQ_PHY_ADDR1			0x00
+#define AQ_PHY_ADDR2			0x01
+#define AQ_PHY_ADDR3			0x02
+#define AQ_PHY_ADDR4			0x03
+#endif
+
+#ifdef CONFIG_TARGET_LX2160ARDB
+#define AQR107_PHY_ADDR1		0x04
+#define AQR107_PHY_ADDR2		0x05
+#define AQR107_IRQ_MASK			0x0C
+#endif
+
+#define CORTINA_PHY_ADDR1		0x0
+#define INPHI_PHY_ADDR1			0x0
+
+#define RGMII_PHY_ADDR1			0x01
+#define RGMII_PHY_ADDR2			0x02
+
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
+#define INPHI_PHY_ADDR2			0x1
+#define SGMII_CARD_PORT1_PHY_ADDR	0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR	0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR	0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR	0x1F
+#endif
+#endif
+
+#endif /* __LX2160_H */
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 0d343da519..9a176f4711 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -575,12 +575,6 @@ int board_late_init(void)
 	return 0;
 }
 
-int checkboard(void)
-{
-	puts("Board: MX6-SabreSD\n");
-	return 0;
-}
-
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
 #include <spl.h>
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 396981605d..23fd619cee 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 {
 	phy_interface_t intf = fm_info_get_enet_if(port);
 	char phy[16];
+	int lane;
+	u8 slot;
 
+	switch (intf) {
 	/* The RGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_RGMII) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
 		fdt_set_phy_handle(fdt, compat, addr, phy);
-	}
-
+		break;
 	/* The SGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_SGMII) {
-		int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
-		u8 slot;
+	case PHY_INTERFACE_MODE_SGMII:
+		lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
 		if (lane < 0)
 			return;
 		slot = lane_to_slot[lane];
@@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
-	}
-
-	if (intf == PHY_INTERFACE_MODE_XGMII) {
+		break;
+	case PHY_INTERFACE_MODE_XGMII:
 		/* XAUI */
-		int lane = serdes_get_first_lane(XAUI_FM1);
+		lane = serdes_get_first_lane(XAUI_FM1);
 		if (lane >= 0) {
 			/* The XAUI PHY is identified by the slot */
 			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
+		break;
+	default:
+		break;
 	}
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
@@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis)
 				fm_info_set_phy_address(i, riser_phy_addr[i]);
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
 			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
 					CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index b64590f9d7..56e6109288 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis)
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 8e2f035874..b034f11d68 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis)
 			break;
 #endif
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (FM1_DTSEC4 == i)
 				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
 			if (FM1_DTSEC5 == i)
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 5044b5695b..aaa3490aaa 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
index c16538850c..e77f3f7146 100644
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis)
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 8a38ac5d4e..3ea9425fd1 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -43,28 +43,21 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int confidx;  /* Default to generic. */
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+
+#define AR8033_DBG_REG_ADDR		0x1d
+#define AR8033_DBG_REG_DATA		0x1e
+#define AR8033_SERDES_REG		0x5
+
+static int productid;  /* Default to generic. */
 static struct vpd_cache vpd;
 
 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
 	PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
-	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -72,31 +65,16 @@ int dram_init(void)
 	return 0;
 }
 
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
-	/* set device address 0x7 */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	/* offset 0x8016: CLK_25M Clock Select */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	/* enable register write, no post increment, address 0x7 */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-	/* set to 125 MHz from local PLL source */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
-
-	/* rgmii tx clock delay enable */
-	/* set debug port address: SerDes Test and System Mode Control */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	/* enable rgmii tx clock delay */
-	/* set the reserved bits to avoid board specific voltage peak issue*/
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
-
-	return 0;
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
-	mx6_rgmii_rework(phydev);
+	/*
+	 * Set reserved bits to avoid board specific voltage peak issue. The
+	 * value is a magic number provided directly by Qualcomm. Note, that
+	 * PHY driver will take control of BIT(8) in this register to control
+	 * TX clock delay, so we do not initialize that bit here.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
+	phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
@@ -127,7 +105,7 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 
 static int is_b850v3(void)
 {
-	return confidx == 3;
+	return productid == VPD_PRODUCT_B850;
 }
 
 static int detect_lcd(struct display_info_t const *dev)
@@ -314,9 +292,6 @@ int overwrite_console(void)
 #define VPD_TYPE_INVALID 0x00
 #define VPD_BLOCK_NETWORK 0x20
 #define VPD_BLOCK_HWID 0x44
-#define VPD_PRODUCT_B850 1
-#define VPD_PRODUCT_B650 2
-#define VPD_PRODUCT_B450 3
 #define VPD_HAS_MAC1 0x1
 #define VPD_HAS_MAC2 0x2
 #define VPD_MAC_ADDRESS_LENGTH 6
@@ -370,15 +345,12 @@ static void process_vpd(struct vpd_cache *vpd)
 
 	switch (vpd->product_id) {
 	case VPD_PRODUCT_B450:
-		env_set("confidx", "1");
 		i210_index = 1;
 		break;
 	case VPD_PRODUCT_B650:
-		env_set("confidx", "2");
 		i210_index = 1;
 		break;
 	case VPD_PRODUCT_B850:
-		env_set("confidx", "3");
 		i210_index = 2;
 		break;
 	}
@@ -398,6 +370,7 @@ static iomux_v3_cfg_t const misc_pads[] = {
 	MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 };
 #define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
+#define PWGIN_IN	IMX_GPIO_NR(4, 14)
 #define WIFI_EN	IMX_GPIO_NR(6, 14)
 
 int board_early_init_f(void)
@@ -412,28 +385,13 @@ int board_early_init_f(void)
 	return 0;
 }
 
-static void set_confidx(const struct vpd_cache* vpd)
-{
-	switch (vpd->product_id) {
-	case VPD_PRODUCT_B450:
-		confidx = 1;
-		break;
-	case VPD_PRODUCT_B650:
-		confidx = 2;
-		break;
-	case VPD_PRODUCT_B850:
-		confidx = 3;
-		break;
-	}
-}
-
 int board_init(void)
 {
 	if (!read_i2c_vpd(&vpd, vpd_callback)) {
 		int ret, rescan;
 
 		vpd.is_read = true;
-		set_confidx(&vpd);
+		productid = vpd.product_id;
 
 		ret = fdtdec_resetup(&rescan);
 		if (!ret && rescan) {
@@ -445,6 +403,9 @@ int board_init(void)
 	gpio_request(SUS_S3_OUT, "sus_s3_out");
 	gpio_direction_output(SUS_S3_OUT, 1);
 
+	gpio_request(PWGIN_IN, "pwgin_in");
+	gpio_direction_input(PWGIN_IN);
+
 	gpio_request(WIFI_EN, "wifi_en");
 	gpio_direction_output(WIFI_EN, 1);
 
@@ -494,6 +455,17 @@ void pmic_init(void)
 	}
 }
 
+static void detect_boot_cause(void)
+{
+	const char *cause = "POR";
+
+	if (is_b850v3())
+		if (!gpio_get_value(PWGIN_IN))
+			cause = "PM_WDOG";
+
+	env_set("bootcause", cause);
+}
+
 int board_late_init(void)
 {
 	process_vpd(&vpd);
@@ -507,6 +479,8 @@ int board_late_init(void)
 	else
 		env_set("videoargs", "video=LVDS-1:1024x768@65");
 
+	detect_boot_cause();
+
 	/* board specific pmic init */
 	pmic_init();
 
@@ -566,16 +540,23 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 int board_fit_config_name_match(const char *name)
 {
+	const char *machine = name;
+
 	if (!vpd.is_read)
 		return strcmp(name, "imx6q-bx50v3");
 
+	if (!strncmp(machine, "Boot ", 5))
+		machine += 5;
+	if (!strncmp(machine, "imx6q-", 6))
+		machine += 6;
+
 	switch (vpd.product_id) {
 	case VPD_PRODUCT_B450:
-		return strcmp(name, "imx6q-b450v3");
+		return strcasecmp(machine, "b450v3");
 	case VPD_PRODUCT_B650:
-		return strcmp(name, "imx6q-b650v3");
+		return strcasecmp(machine, "b650v3");
 	case VPD_PRODUCT_B850:
-		return strcmp(name, "imx6q-b850v3");
+		return strcasecmp(machine, "b850v3");
 	default:
 		return -1;
 	}
diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c
index 421fee5922..c28d2c03cf 100644
--- a/board/ge/common/vpd_reader.c
+++ b/board/ge/common/vpd_reader.c
@@ -209,7 +209,7 @@ int read_i2c_vpd(struct vpd_cache *cache,
 	u8 *data;
 	int size;
 
-	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev);
+	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev);
 	if (ret)
 		return ret;
 
diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig
index 05d65445e4..23b2af4821 100644
--- a/board/intel/edison/Kconfig
+++ b/board/intel/edison/Kconfig
@@ -31,5 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_TANGIER
 	select BOARD_LATE_INIT
 	select MD5
+	imply BINMAN
 
 endif
diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c
index 652f975515..11e7f74e47 100644
--- a/board/intel/edison/edison.c
+++ b/board/intel/edison/edison.c
@@ -3,15 +3,10 @@
  * Copyright (c) 2017 Intel Corporation
  */
 #include <common.h>
-#include <dwc3-uboot.h>
 #include <env.h>
 #include <init.h>
 #include <mmc.h>
 #include <u-boot/md5.h>
-#include <usb.h>
-#include <watchdog.h>
-
-#include <linux/usb/gadget.h>
 
 #include <asm/cache.h>
 #include <asm/pmu.h>
@@ -27,36 +22,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-static struct dwc3_device dwc3_device_data = {
-	.maximum_speed = USB_SPEED_HIGH,
-	.base = CONFIG_SYS_USB_OTG_BASE,
-	.dr_mode = USB_DR_MODE_PERIPHERAL,
-	.index = 0,
-};
-
-int usb_gadget_handle_interrupts(int controller_index)
-{
-	dwc3_uboot_handle_interrupt(controller_index);
-	WATCHDOG_RESET();
-	return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	if (index == 0 && init == USB_INIT_DEVICE)
-		return dwc3_uboot_init(&dwc3_device_data);
-	return -EINVAL;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	if (index == 0 && init == USB_INIT_DEVICE) {
-		dwc3_uboot_exit(index);
-		return 0;
-	}
-	return -EINVAL;
-}
-
 static void assign_serial(void)
 {
 	struct mmc *mmc = find_mmc_device(0);
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index b1147f2e1a..e06f05bfa4 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
index 92e3d40a1b..22a193d8fc 100644
--- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c
+++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c
index 85988acb24..4ad4ee69c7 100644
--- a/board/st/stm32f469-discovery/stm32f469-discovery.c
+++ b/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c
index 0484c3c250..0b5afa05ac 100644
--- a/board/st/stm32h743-disco/stm32h743-disco.c
+++ b/board/st/stm32h743-disco/stm32h743-disco.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c
index 0484c3c250..0b5afa05ac 100644
--- a/board/st/stm32h743-eval/stm32h743-eval.c
+++ b/board/st/stm32h743-eval/stm32h743-eval.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  */
 
 #include <common.h>
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 8a3ce0a6f5..d3cffdd770 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -827,11 +827,22 @@ const char *env_ext4_get_intf(void)
 
 const char *env_ext4_get_dev_part(void)
 {
+	static char *const env_dev_part =
+#ifdef CONFIG_ENV_EXT4_DEVICE_AND_PART
+		CONFIG_ENV_EXT4_DEVICE_AND_PART;
+#else
+		"";
+#endif
 	static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
+
+	if (strlen(env_dev_part) > 0)
+		return env_dev_part;
+
 	u32 bootmode = get_bootmode();
 
 	return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
 }
+
 int mmc_get_env_dev(void)
 {
 	u32 bootmode = get_bootmode();
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 9263b0f51f..2ed66261d2 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -37,6 +37,29 @@ static void setup_iomux_uart(void)
 	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_quadplus = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* QP has one A72 core disabled */
+		is_quadplus = ((val >> 4) & 0x3) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	if (is_quadplus)
+		/* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
+		*phys_sdram_2_size = 0x0UL;
+	else
+		*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
 int board_early_init_f(void)
 {
 	sc_pm_clock_rate_t rate = SC_80MHZ;
diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig
new file mode 100644
index 0000000000..ee61e09736
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8X
+
+config SYS_BOARD
+	default "apalis-imx8x"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-imx8x"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS
new file mode 100644
index 0000000000..5272154447
--- /dev/null
+++ b/board/toradex/apalis-imx8x/MAINTAINERS
@@ -0,0 +1,10 @@
+Apalis iMX8X
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8x-apalis.dts
+F:	arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi
+F:	board/toradex/apalis-imx8x/
+F:	configs/apalis-imx8x_defconfig
+F:	doc/board/toradex/apalis-imx8x.rst
+F:	include/configs/apalis-imx8x.h
diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile
new file mode 100644
index 0000000000..9d6e85b742
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += apalis-imx8x.o
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
new file mode 100644
index 0000000000..58c62d0a65
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c
new file mode 100644
index 0000000000..739d2e5155
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate;
+	sc_err_t err = 0;
+
+	/*
+	 * This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART3 clock root to 80 MHz and enable it */
+	rate = SC_80MHZ;
+	err = sc_pm_setup_uart(SC_R_UART_1, rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis iMX8X\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Apalis iMX8X");
+#endif
+
+	return 0;
+}
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 4a2707e771..fde4d92dc3 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
 Apalis iMX6
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:      https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
index 49c2df7ab2..3a2cf4606e 100644
--- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -11,7 +11,9 @@
 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
+/* TRISTATE here means output driver is tri-stated */ \
 		.tristate	= PMUX_TRI_##_tri,		\
+/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
 		.io		= PMUX_PIN_##_io,		\
 		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
 		.od		= PMUX_PIN_OD_DEFAULT,		\
@@ -118,7 +120,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
 	DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
 	DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
 	DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
-	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+	/* UARTD RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
 	DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
 	DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
 	DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
@@ -187,12 +190,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
 	LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
 	LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 	LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+	/* UARTB RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
 	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
 	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
 	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
 	DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
-	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+	/* UARTC RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
 	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
 	DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
 	DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),
diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
index 4107d29876..899b1ff555 100644
--- a/board/toradex/colibri-imx6ull/MAINTAINERS
+++ b/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX6ULL
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index f981c11a37..da081e30be 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -39,6 +39,29 @@ static void setup_iomux_uart(void)
 	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
 int board_early_init_f(void)
 {
 	sc_pm_clock_rate_t rate;
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index 76f9446bba..2cbf65433d 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX6
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:      https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index 61a504487a..3d7d010d8a 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX7
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS
index 2a8e6fb74b..61fbd2c1e0 100644
--- a/board/toradex/colibri_t20/MAINTAINERS
+++ b/board/toradex/colibri_t20/MAINTAINERS
@@ -1,5 +1,5 @@
 COLIBRI_T20
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t20/
 F:	include/configs/colibri_t20.h
diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS
index 00c03c89b8..ded9e28295 100644
--- a/board/toradex/colibri_t30/MAINTAINERS
+++ b/board/toradex/colibri_t30/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri T30
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t30/
 F:	include/configs/colibri_t30.h
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index c5562f6d57..20cbb75a36 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -58,6 +58,17 @@ void pinmux_init(void)
 }
 
 /*
+ * Disable RS232 serial transceiver ForceOFF# pins on Iris
+ */
+void gpio_early_init_uart(void)
+{
+	gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13");
+	gpio_direction_output(TEGRA_GPIO(X, 6), 1);
+	gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14");
+	gpio_direction_output(TEGRA_GPIO(X, 7), 1);
+}
+
+/*
  * Enable AX88772B USB to LAN controller
  */
 void pin_mux_usb(void)
diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
index bdbbf5e49a..5ac1a6da97 100644
--- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
+++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
@@ -11,7 +11,9 @@
 		.pingrp		= PMUX_PINGRP_##_pingrp,	\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
+/* TRISTATE here means output driver is tri-stated */ \
 		.tristate	= PMUX_TRI_##_tri,		\
+/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
 		.io		= PMUX_PIN_##_io,		\
 		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
 		.od		= PMUX_PIN_OD_DEFAULT,		\
@@ -178,14 +180,16 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
 	LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 	LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 	LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
-	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
-	DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
-	DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
-	DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+	/* UARTC RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT),
+
 	DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
 	DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
 	DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
@@ -204,11 +208,11 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
 	DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
 	DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
 	DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
+	/* UARTB RX, make sure we don't get input form a floating Pin */
+	DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT),
 	DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
 	DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT),
 
-
 	/* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
 	DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT),
 	DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
@@ -268,10 +272,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
 	DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
 
 	DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
-	DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
-	DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT),
 
 	/* LAN_RESET */
 	DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index f94cc0fbe2..c6627654a2 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri VFxx
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index bf27b2fa66..adab0a0802 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -16,7 +16,8 @@
 	defined(CONFIG_TARGET_COLIBRI_IMX6) || \
 	defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
 	defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
-	defined(CONFIG_TARGET_VERDIN_IMX8MN)
+	defined(CONFIG_TARGET_VERDIN_IMX8MN) || \
+	defined(CONFIG_TARGET_VERDIN_IMX8MP)
 #include <asm/arch/sys_proto.h>
 #else
 #define is_cpu_type(cpu) (0)
@@ -137,8 +138,12 @@ const char * const toradex_modules[] = {
 	[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
 	[54] = "Apalis iMX8 DualXPlus 1GB",
 	[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
-	[56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */
+	[56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */
 	[57] = "Verdin iMX8M Mini DualLite 1GB",
+	[58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT",
+	[59] = "Verdin iMX8M Mini Quad 2GB IT",
+	[60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
+	[61] = "Verdin iMX8M Plus Quad 2GB",
 };
 
 const char * const toradex_carrier_boards[] = {
@@ -361,21 +366,15 @@ static int get_cfgblock_interactive(void)
 
 	if (cpu_is_pxa27x())
 		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
-#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN)
-	else
-		sprintf(message, "Is the module an IT version? [y/N] ");
-
-	len = cli_readline(message);
-	it = console_buffer[0];
-#else
 	else
 		it = 'y';
-#endif
 
 #if defined(CONFIG_TARGET_APALIS_IMX8) || \
 		defined(CONFIG_TARGET_APALIS_IMX8X) || \
 		defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
-		defined(CONFIG_TARGET_COLIBRI_IMX8X)
+		defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MP)
 	sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
 	len = cli_readline(message);
 	wb = console_buffer[0];
@@ -424,12 +423,6 @@ static int get_cfgblock_interactive(void)
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
 	else if (!strcmp("imx7s", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7S;
-	else if (is_cpu_type(MXC_CPU_IMX8MM))
-		tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
-	else if (is_cpu_type(MXC_CPU_IMX8MMDL))
-		tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
-	else if (is_cpu_type(MXC_CPU_IMX8MN))
-		tdx_hw_tag.prodid = VERDIN_IMX8MNSL;
 	else if (is_cpu_type(MXC_CPU_IMX8QM)) {
 		if (it == 'y' || it == 'Y') {
 			if (wb == 'y' || wb == 'Y')
@@ -465,6 +458,23 @@ static int get_cfgblock_interactive(void)
 				tdx_hw_tag.prodid = COLIBRI_IMX8DX;
 		}
 #endif
+	} else if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
+	} else if (is_cpu_type(MXC_CPU_IMX8MM)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MN)) {
+		tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MP)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
 	} else if (!strcmp("tegra20", soc)) {
 		if (it == 'y' || it == 'Y')
 			if (gd->ram_size == 0x10000000)
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 8f91d9aec6..9debd5f046 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -75,9 +75,13 @@ enum {
 	COLIBRI_IMX8DX,
 	APALIS_IMX8QXP,
 	APALIS_IMX8DXP,
-	VERDIN_IMX8MMQ_WIFI_BT_IT,
-	VERDIN_IMX8MNSL,
+	VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */
+	VERDIN_IMX8MNQ_WIFI_BT,
 	VERDIN_IMX8MMDL,
+	VERDIN_IMX8MPQ_WIFI_BT_IT,
+	VERDIN_IMX8MMQ_IT,
+	VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */
+	VERDIN_IMX8MPQ,
 };
 
 enum {
diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS
index 2495696e9d..08c370178c 100644
--- a/board/toradex/verdin-imx8mm/MAINTAINERS
+++ b/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -1,5 +1,5 @@
 Verdin iMX8M Mini
-M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+M:	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
 W:	https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
 S:	Maintained
 F:	arch/arm/dts/imx8mm-verdin.dts
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index cc78c5666b..72e2e09e25 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -21,12 +21,16 @@
 #include <dm/uclass.h>
 #include <dm/uclass-internal.h>
 #include <hang.h>
+#include <i2c.h>
 #include <power/bd71837.h>
+#include <power/pca9450.h>
 #include <power/pmic.h>
 #include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define I2C_PMIC_BUS_ID        1
+
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -101,33 +105,29 @@ int power_init_board(void)
 	struct udevice *dev;
 	int ret;
 
-	ret = pmic_get("pmic@4b", &dev);
-	if (ret == -ENODEV) {
-		puts("No pmic\n");
-		return 0;
-	}
-	if (ret != 0)
-		return ret;
+	if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+		ret = pmic_get("pmic", &dev);
+		if (ret == -ENODEV) {
+			puts("No pmic found\n");
+			return ret;
+		}
 
-	/* decrease RESET key long push time from the default 10s to 10ms */
-	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+		if (ret != 0)
+			return ret;
 
-	/* unlock the PMIC regs */
-	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+		/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+		pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
 
-	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
-	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+		/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
 
-	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
-	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+		/* set WDOG_B_CFG to cold reset */
+		pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
 
-#ifndef CONFIG_IMX8M_LPDDR4
-	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
-	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
-#endif
+		pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
 
-	/* lock the PMIC regs */
-	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+		return 0;
+	}
 
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 66950ed218..7cfae8767c 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -8,12 +8,22 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <i2c.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <micrel.h>
 
+#include "../common/tdx-cfg-block.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define I2C_PMIC	0
+
+enum pcb_rev_t {
+	PCB_VERSION_1_0,
+	PCB_VERSION_1_1
+};
+
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {
@@ -104,8 +114,79 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
+static enum pcb_rev_t get_pcb_revision(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	u8 is_bd71837 = 0;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus);
+	if (!ret)
+		ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev);
+	if (!ret)
+		ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1);
+
+	/* BD71837_REV, High Nibble is major version, fix 1010 */
+	is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0);
+	return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1;
+}
+
+static void select_dt_from_module_version(void)
+{
+	char variant[32];
+	char *env_variant = env_get("variant");
+	int is_wifi = 0;
+
+	if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+		/*
+		 * If we have a valid config block and it says we are a
+		 * module with Wi-Fi/Bluetooth make sure we use the -wifi
+		 * device tree.
+		 */
+		is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT);
+	}
+
+	switch (get_pcb_revision()) {
+	case PCB_VERSION_1_0:
+		printf("Detected a V1.0 module\n");
+		if (is_wifi)
+			strncpy(&variant[0], "wifi", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi", sizeof(variant));
+		break;
+	default:
+		if (is_wifi)
+			strncpy(&variant[0], "wifi-v1.1", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant));
+		break;
+	}
+
+	if (strcmp(variant, env_variant)) {
+		printf("Setting variant to %s\n", variant);
+		env_set("variant", variant);
+
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			env_save();
+	}
+}
+
 int board_late_init(void)
 {
+	select_dt_from_module_version();
+
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
 	return 0;
 }
 
diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c
index d8e383d323..360be758bb 100644
--- a/board/variscite/dart_6ul/dart_6ul.c
+++ b/board/variscite/dart_6ul/dart_6ul.c
@@ -12,8 +12,11 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
+#include <dm.h>
 #include <fsl_esdhc_imx.h>
+#include <i2c_eeprom.h>
 #include <linux/bitops.h>
+#include <malloc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <usb.h>
@@ -222,9 +225,108 @@ int board_init(void)
 	return 0;
 }
 
+/* length of strings stored in the eeprom */
+#define DART6UL_PN_LEN   16
+#define DART6UL_ASSY_LEN 16
+#define DART6UL_DATE_LEN 12
+
+/* eeprom content, 512 bytes */
+struct dart6ul_info {
+	u32 magic;
+	u8 partnumber[DART6UL_PN_LEN];
+	u8 assy[DART6UL_ASSY_LEN];
+	u8 date[DART6UL_DATE_LEN];
+	u32 custom_addr_val[32];
+	struct cmd {
+		u8 addr;
+		u8 index;
+	} custom_cmd[150];
+	u8 res[33];
+	u8 som_info;
+	u8 ddr_size;
+	u8 crc;
+} __attribute__ ((__packed__));
+
+#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3)
+#define DART6UL_INFO_WIFI_GET(n)    ((n) >> 2 & 0x1)
+#define DART6UL_INFO_REV_GET(n)     ((n) >> 3 & 0x3)
+#define DART6UL_DDRSIZE_IN_MIB(n)   ((n) << 8)
+#define DART6UL_INFO_MAGIC          0x32524156
+
+static const char *som_info_storage_to_str(u8 som_info)
+{
+	switch (DART6UL_INFO_STORAGE_GET(som_info)) {
+	case 0x0: return "none (SD only)";
+	case 0x1: return "NAND";
+	case 0x2: return "eMMC";
+	default: return "unknown";
+	}
+}
+
+static const char *som_info_rev_to_str(u8 som_info)
+{
+	switch (DART6UL_INFO_REV_GET(som_info)) {
+	case 0x0: return "2.4G";
+	case 0x1: return "5G";
+	default: return "unknown";
+	}
+}
+
 int checkboard(void)
 {
-	puts("Board: Variscite DART-6UL Evaluation Kit\n");
+	const char *path = "eeprom0";
+	struct dart6ul_info *info;
+	struct udevice *dev;
+	int ret, off;
+
+	off = fdt_path_offset(gd->fdt_blob, path);
+	if (off < 0) {
+		printf("%s: fdt_path_offset() failed: %d\n", __func__, off);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	info = malloc(sizeof(struct dart6ul_info));
+	if (!info)
+		return -ENOMEM;
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
+			      sizeof(struct dart6ul_info));
+	if (ret) {
+		printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
+		free(info);
+		return ret;
+	}
+
+	if (info->magic != DART6UL_INFO_MAGIC) {
+		printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
+		       info->magic, DART6UL_INFO_MAGIC);
+		/* do not fail if the content is invalid */
+		free(info);
+		return 0;
+	}
+
+	/* make sure strings are null terminated */
+	info->partnumber[DART6UL_PN_LEN - 1] = '\0';
+	info->assy[DART6UL_ASSY_LEN - 1] = '\0';
+	info->date[DART6UL_DATE_LEN - 1] = '\0';
+
+	printf("Board: PN: %s, Assy: %s, Date: %s\n"
+	       "       Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n",
+	       info->partnumber,
+	       info->assy,
+	       info->date,
+	       som_info_storage_to_str(info->som_info),
+	       DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no",
+	       DART6UL_DDRSIZE_IN_MIB(info->ddr_size),
+	       som_info_rev_to_str(info->som_info));
+
+	free(info);
 
 	return 0;
 }