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| author | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:26:33 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-07-08 19:26:33 +0200 |
| commit | 50cd93b25033764dcda9bb47aa68be778f94d36e (patch) | |
| tree | b8606a377b805952d533300dfa1e98e42951678e /board | |
| parent | 8246ff864de38935ff34108856a37a2caf6cbefc (diff) | |
| parent | d702b0811df53a1fc2d8049e35431e4591d093c6 (diff) | |
| download | u-boot-50cd93b25033764dcda9bb47aa68be778f94d36e.tar.gz u-boot-50cd93b25033764dcda9bb47aa68be778f94d36e.tar.xz u-boot-50cd93b25033764dcda9bb47aa68be778f94d36e.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
ARM: cache: Move the cp15 CR register read before flushing the cache.
ARM: introduce arch_early_init_r()
PXA: Enable CONFIG_PREBOOT on zipitz2
ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
No need to define CONFIG_ARCH_CPU_INIT.
add new board vl_ma2sc
MTD: SPEAr SMI: Add write support for length < 4 bytes
i2c: designware_i2c.c: Add support for the "i2c probe" command
rtc/m41t62: Add support for M41T82 with HT (Halt Update)
SPL: ARM: spear: Add SPL support for SPEAr600 platform
Makefile: Add u-boot.spr build target (SPEAr)
SPL: ARM: spear: Remove some objects from SPL build
SPL: lib/Makefile: Add crc32.c to SPL build
SPL: common/Makefile: Add image.c to SPL build
arm: Don't use printf() in SPL builds
GPIO: Add SPEAr GPIO driver
net: Multiple updates/enhancements to designware.c
cleanup/SPEAr: Define configuration flags more elegantly
cleanup/SPEAr: Remove unnecessary parenthesis
SPEAr: Correct SoC ID offset in misc configuration space
SPEAr: explicitly select clk src for UART
SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
SPEAr: Enable dcache for fast file transfer
SPEAr: Enable autoneg for ethernet
SPEAr: Enable udc and usb-console support only for usbtty configuration
SPEAr: Enable usb device high speed support
SPEAr: Initialize SNOR in early_board_init_f
SPEAr: Change the default environment variables
SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
SPEAr: Add configuration options for spear3xx and spear6xx boards
SPEAr: Add basic arch related support for SPEAr SoCs
SPEAr: Add interface information in initialization
SPEAr: Add macb driver support for spear310 and spear320
SPEAr: Configure network support for spear SoCs
SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
SPEAr: Eliminate dependency on Xloader table
SPEAr: Fix ARM relocation support
st_smi: Fixed page size for Winbond W25Q128FV flash
st_smi: Change timeout loop implementation
st_smi: Fix bug in flash_print_info()
st_smi: Change the flash probing method
st_smi: Removed no needed dependency on ST_M25Pxx_ID
st_smi: Fix smi read status
st_smi: Move status register read before modifying ctrl register
st_smi: Read status until timeout happens
st_smi: Enhance the error handling
st_smi: Change SMI timeout values
st_smi: Return error in case TFF is not set
st_smi: Add support for SPEAr SMI driver
mtd/NAND: Remove obsolete SPEAr specific NAND drivers
SPEAr: Configure FSMC driver for NAND interface
mtd/NAND: Add FSMC driver support
arm/km: remove calls to kw_gpio_* in board_early_init_f
arm/km: add implementation for read_dip_switch
arm/km: support the 2 PCIe fpga resets
arm/km: skip FPGA config when already configured
arm/km: redefine piggy 4 reg names to avoid conflicts
arm/km: cleanup km_kirkwood boards
arm/km: enable BOCO2 FPGA download support
arm/km: remove portl2.h and use km_kirkwood instead
arm/km: convert mgcoge3un target to km_kirkwood
arm/km: add kmcoge5un board support
arm/km: add kmnusa board support
arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
cm-t35: fix incorrect NAND_ECC layout selection
ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
ARM: OMAP4/5: Move USB pads to essential list.
ARM: OMAP4/5: Move USB clocks to essential group.
ARM: OMAP4/5: Move gpmc clocks to essential group.
ARM: OMAP4+: Move external phy initialisations to arch specific place.
omap4: Use a smaller M,N couple for IVA DPLL
da850/omap-l138: Enable auto negotiation in RMII mode
omap: am33xx: accomodate input clocks other than 24 Mhz
omap: emif: fix bug in manufacturer code test
omap: emif: deal with rams that return duplicate mr data on all byte lanes
OMAP4+: Force DDR in self-refresh after warm reset
OMAP4+: Handle sdram init after warm reset
ARM: OMAP3+: Detect reset type
arm: bugfix: Move vector table before jumping relocated code
Kirkwood: Add support for Ka-Ro TK71
arm/km: use spi claim bus to switch between SPI and NAND
arm/kirkwood: protect the ENV_SPI #defines
ARM: don't probe PHY address for LaCie boards
lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
lacie_kw: fix SDRAM banks number for net2big_v2
Kirkwood: add lschlv2 and lsxhl board support
net: add helper to generate random mac address
net: use common rand()/srand() functions
lib: add rand() function
kwboot: boot kirkwood SoCs over a serial link
kw_spi: add weak functions board_spi_claim/release_bus
kw_spi: support spi_claim/release_bus functions
kw_spi: backup and reset the MPP of the chosen CS pin
kirkwood: fix calls to kirkwood_mpp_conf
kirkwood: add save functionality kirkwood_mpp_conf function
km_arm: use filesize for erase in update command
arm/km: enable mii cmd
arm/km: remove CONFIG_RESET_PHY_R
arm/km: change maintainer for mgcoge3un
arm/km: fix wrong comment in SDRAM config for mgcoge3un
arm/km: use ARRAY_SIZE macro
arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
arm/km: add piggy mac adress offset for mgcoge3un
arm/km: add board type to boards.cfg
AT91SAM9*: Change kernel address in dataflash to match u-boot's size
ATMEL/PIO: Enable new feature of PIO on Atmel device
ehci-atmel: fix compiler warning
AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
Atmel : usb : add EHCI driver for Atmel SoC
Fix: AT91SAM9263 nor flash usage
Fix: broken boot message at serial line on AT91SAM9263-EK board
i.MX6 USDHC: Use the ESDHC clock
mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
i.MX28: Add function to adjust memory parameters
mx28evk: Fix PSWITCH key position
mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove unused CONFIG_MII_GASKET
mx6: Avoid writing to read-only bits in imximage.cfg
m28evk: use same notation to alloc the 128kB stack
...
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board')
81 files changed, 4044 insertions, 617 deletions
diff --git a/board/spear/spear310/config.mk b/board/BuS/vl_ma2sc/Makefile index f8a6bdb976..1cadfb30e0 100644 --- a/board/spear/spear310/config.mk +++ b/board/BuS/vl_ma2sc/Makefile @@ -1,6 +1,10 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009-2012 +# Jens Scharsig <esw@bus-elekronik.de> +# BuS Elektronik GmbH & Co. KG # # See file CREDITS for list of people who contributed to this # project. @@ -12,7 +16,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -21,24 +25,24 @@ # MA 02111-1307 USA # -######################################################################### +include $(TOPDIR)/config.mk -CONFIG_SYS_TEXT_BASE = 0x00700000 +LIB = $(obj)lib$(BOARD).o -ALL-y += $(obj)u-boot.img +COBJS += vl_ma2sc.o -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c new file mode 100644 index 0000000000..62ed6fb432 --- /dev/null +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw@bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/sizes.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_common.h> +#include <lcd.h> +#include <i2c.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static void vl_ma2sc_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + /* Configure RDY/BSY */ +#ifdef CONFIG_SYS_NAND_READY_PIN + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void vl_ma2sc_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 240, + .vl_clk = 6500000, + .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED | + ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVVD_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5), + .vl_tft = 1, + .vl_hsync_len = 5, /* Horiz Sync Pulse Width */ + .vl_left_margin = 68, /* horiz back porch */ + .vl_right_margin = 20, /* horiz front porch */ + .vl_vsync_len = 2, /* vert Sync Pulse Width */ + .vl_upper_margin = 18, /* vert back porch */ + .vl_lower_margin = 4, /* vert front porch */ + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +static void vl_ma2sc_lcd_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ + at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ + at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ + at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ + + at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; +} +#endif /* Config LCD */ + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + at91_seriald_hw_init(); + + return 0; +} +#endif + +int board_init(void) +{ + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + pin = 0x1F000001; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + writel((1 << 25), &pio->pioa.codr); + + pin = 0x1F000100; + writel(pin, &pio->piob.idr); + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.codr); + writel((1 << 24), &pio->piob.sodr); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + + pin = 0x0000000F; /* HWversion als Input */ + writel(pin, &pio->piod.idr); + writel(pin, &pio->piod.puer); + writel(pin, &pio->piod.per); + writel(pin, &pio->piod.odr); + writel(pin, &pio->piod.owdr); + + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); + writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); + writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); + writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); + +#ifdef CONFIG_CMD_NAND + vl_ma2sc_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + vl_ma2sc_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + vl_ma2sc_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + uchar buffer[8]; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + buffer[0] = 0x04; + buffer[1] = 0x00; + if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) + puts("error reseting rtc clock\n\0"); + + /* read hardware version */ + + pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; + printf("Board: revision %c\n", pin); + buffer[0] = pin; + buffer[1] = 0; + setenv("revision", (char *) buffer); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); +#endif + return rc; +} + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u8 sda = (1<<4); + u8 scl = (1<<5); + + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + pin = sda | scl; + writel(pin, &pio->piob.idr); /* Disable Interupt */ + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.sodr); +} +#endif + +void watchdog_reset(void) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin = 0x1; /* PA0 */ + + if ((readl(&pio->pioa.odsr) & pin) > 0) + writel(pin, &pio->pioa.codr); + else + writel(pin, &pio->pioa.sodr); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +/*---------------------------------------------------------------------------*/ + +int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + int col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ + + pins = 0x1F000000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.oer); + writel(pins, &pio->pioa.sodr); + + pinz = 0x1F000000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.sodr); + + for (row = 0; row < 5; row++) { + for (col = 0; col < 5; col++) { + writel((0x01000000 << col), &pio->piob.sodr); + writel((0x01000000 << row), &pio->pioa.codr); + printf("LED Test %d x %d\n", row, col); + udelay(1000000); + writel(pinz, &pio->piob.codr); + writel(pins, &pio->pioa.sodr); + } + } + return rcode; +} + +void poweroff(void) +{ + watchdog_reset(); + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ + udelay(100); + while (1) + watchdog_reset(); +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + poweroff(); + return rcode; +} + +int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + u32 freq; + u32 durate; + int rcode = 1; + + freq = 1000; + durate = 2; + switch (argc) { + case 3: + durate = simple_strtoul(argv[2], NULL, 10); + case 2: + freq = simple_strtoul(argv[1], NULL, 10); + case 1: + break; + default: + cmd_usage(cmdtp); + rcode = 1; + break; + } + durate = durate * freq; + freq = 500000 / freq; + for (i = 0; i < durate; i++) { + at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ + udelay(freq); + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + udelay(freq); + } + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + return rcode; +} + +int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + u32 col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + writel((1 << ATMEL_ID_PIOA), &pmc->pcer); + + pins = 0x001F0000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.odr); + + pinz = 0x000F0000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.codr); + + while (1) { + col = 0; + for (row = 0; row < 4; row++) { + writel((0x00010000 << row), &pio->piob.sodr); + udelay(10000); + col <<= 4; + col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; + writel(pinz, &pio->piob.codr); + } + printf("Matix: "); + for (row = 0; row < 16; row++) { + printf("%1.1d", col & 1); + col >>= 1; + } + printf(" SP %d\r ", + 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { + /* SHUTDOWN */ + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) + row++; + udelay(100); + } + udelay(100000); + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { + row++; + udelay(1000); + } + } + poweroff(); + while (1) + ; + } + } + return rcode; +} + +/*****************************************************************************/ + +U_BOOT_CMD( + ledtest, 1, 0, do_ledtest, + "test ledmatrix", + "\n" + ); + +U_BOOT_CMD( + keytest, 1, 0, do_keytest, + "test keymatix and special keys, poweroff on pressing ON key", + "\n" + ); + +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "power off", + "\n" + ); + +U_BOOT_CMD( + beep, 3, 0, do_beep, + "[freq [duration]]", + "freq frequence of beep\nduration duration of beep\n" + ); + +/*****************************************************************************/ diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index dc5350dc28..78d0edc66d 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -20,34 +20,25 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) -void mv_phy_88e1116_init(const char *name) +void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; - u16 devadr; if (miiphy_set_current_dev(name)) return; - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); - printf("88E1116 Initialized on %s\n", name); + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1116 Initialized on %s\n", name); } #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 82a9522236..2edd5abbcd 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -11,7 +11,7 @@ #define _LACIE_COMMON_H #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -void mv_phy_88e1116_init(const char *name); +void mv_phy_88e1116_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 1b33875f2f..4a9b30834a 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -96,6 +96,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index d0b4adffc0..0e06c29153 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -75,7 +75,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -109,7 +109,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index fbf020fde1..68e8a770c7 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -73,7 +73,7 @@ int board_early_init_f(void) MPP33_GPIO, /* Fan speed (bit 2) */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -107,7 +107,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 31b73c98b0..d6497aaa07 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -99,7 +99,7 @@ int board_early_init_f(void) MPP49_GPIO, /* Wifi AP LED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 057c558682..f5c1c3cfd9 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, /* B_GLED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 4c41f3b2ef..43852f6b24 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -98,7 +98,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 2a10e69faf..d48f05a048 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -102,7 +102,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 9c768bf595..1fd7677dcb 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 71e6793098..688d3086d4 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 38473e5808..fc88520b2d 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -100,7 +100,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c index 2629c67186..9ec054f22b 100644 --- a/board/atmel/at91sam9260ek/partition.c +++ b/board/atmel/at91sam9260ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c index c739b116bf..51cac77d4f 100644 --- a/board/atmel/at91sam9261ek/partition.c +++ b/board/atmel/at91sam9261ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 41ec752570..60ff1c0cd3 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -254,6 +254,7 @@ int board_early_init_f(void) (1 << ATMEL_ID_PIOCDE), &pmc->pcer); + at91_seriald_hw_init(); return 0; } @@ -267,7 +268,6 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c index 7e1d46f530..d48fab791c 100644 --- a/board/atmel/at91sam9263ek/partition.c +++ b/board/atmel/at91sam9263ek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c index 7e1d46f530..d48fab791c 100644 --- a/board/atmel/at91sam9rlek/partition.c +++ b/board/atmel/at91sam9rlek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/spear/spear320/config.mk b/board/buffalo/lsxl/Makefile index f8a6bdb976..36f2560ba9 100644 --- a/board/spear/spear320/config.mk +++ b/board/buffalo/lsxl/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> # # See file CREDITS for list of people who contributed to this # project. @@ -12,33 +12,33 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA # -######################################################################### +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := lsxl.o -CONFIG_SYS_TEXT_BASE = 0x00700000 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -ALL-y += $(obj)u-boot.img +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif +sinclude $(obj).depend -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +######################################################################### diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg new file mode 100644 index 0000000000..2b9b3cd1b7 --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lschl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543000 +# bit3-0: 0 required +# bit4: 0, addr/cmd in same cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x3302444F +# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 4, 5 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 0, 16 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 3, 4 cycle tRRD +# bit31-28: 3, 4 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000823 +# bit6-0: 0x23, 35 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x00000009 +# bit1-0: 1, Cs0width=x16 +# bit3-2: 2, Cs0size=512Mbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000042 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) +# bit5-3: 0 required +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x03FFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x03, Size (i.e. 64MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x003C0000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 +# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg new file mode 100644 index 0000000000..8a94b6c718 --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B9B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543010 +# bit3-0: 0 required +# bit4: 1, T2 mode, addr/cmd are driven for two cycles +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x22125441 +# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 5, 6 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 1, 18 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 2, 3 cycle tRRD +# bit31-28: 2, 3 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000832 +# bit6-0: 0x32, 50 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x0000000C +# bit1-0: 0, Cs0width=x8 +# bit3-2: 3, Cs0size=1Gbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000006 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) +# bit5-3: 0 required +# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x0FFFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x0f, Size (i.e. 256MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x00010000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 +# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c new file mode 100644 index 0000000000..fe155112c9 --- /dev/null +++ b/board/buffalo/lsxl/lsxl.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> + * + * Based on sheevaplug/sheevaplug.c by + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <netdev.h> +#include <miiphy.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> +#include <spi_flash.h> + +#include "lsxl.h" + +/* + * Rescue mode + * + * Selected by holding the push button for 3 seconds, while powering on + * the device. + * + * These linkstations don't have a (populated) serial port. There is no + * way to access an (unmodified) board other than using the netconsole. If + * you want to recover from a bad environment setting or an empty environment, + * you can do this only with a working network connection. Therefore, a random + * ethernet address is generated if none is set and a DHCP request is sent. + * After a successful DHCP response is received, the network settings are + * configured and the ncip parameter is set to the serverip. Eg. for a working + * resuce mode, you should set 'next-server' to the host where the netconsole + * client is started. + * Additionally, the bootsource is set to 'rescue'. + */ + +#ifndef CONFIG_ENV_OVERWRITE +# error "You need to set CONFIG_ENV_OVERWRITE" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); + + /* + * Multi-Purpose Pins Functionality configuration + * These strappings are taken from the original vendor uboot port. + */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_UART0_RXD, + MPP5_UART0_TXD, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_GPIO, + MPP9_GPIO, + MPP10_GPO, /* HDD power */ + MPP11_GPIO, /* USB Vbus enable */ + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_GPO, /* fan speed high */ + MPP19_GPO, /* fan speed low */ + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* function LED */ + MPP37_GPIO, /* alarm LED */ + MPP38_GPIO, /* info LED */ + MPP39_GPIO, /* power LED */ + MPP40_GPIO, /* fan alarm */ + MPP41_GPIO, /* funtion button */ + MPP42_GPIO, /* power switch */ + MPP43_GPIO, /* power auto switch */ + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, /* function red LED */ + MPP49_GPIO, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +#define LED_OFF 0 +#define LED_ALARM_ON 1 +#define LED_ALARM_BLINKING 2 +#define LED_POWER_ON 3 +#define LED_POWER_BLINKING 4 +#define LED_INFO_ON 5 +#define LED_INFO_BLINKING 6 + +static void __set_led(int blink_alarm, int blink_info, int blink_power, + int value_alarm, int value_info, int value_power) +{ + kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm); + kw_gpio_set_blink(GPIO_INFO_LED, blink_info); + kw_gpio_set_blink(GPIO_POWER_LED, blink_power); + kw_gpio_set_value(GPIO_ALARM_LED, value_alarm); + kw_gpio_set_value(GPIO_INFO_LED, value_info); + kw_gpio_set_value(GPIO_POWER_LED, value_power); +} + +static void set_led(int state) +{ + switch (state) { + case LED_OFF: + __set_led(0, 0, 0, 0, 0, 0); + break; + case LED_ALARM_ON: + __set_led(0, 0, 0, 0, 1, 1); + break; + case LED_ALARM_BLINKING: + __set_led(1, 0, 0, 1, 1, 1); + break; + case LED_INFO_ON: + __set_led(0, 0, 0, 1, 0, 1); + break; + case LED_INFO_BLINKING: + __set_led(0, 1, 0, 1, 1, 1); + break; + case LED_POWER_ON: + __set_led(0, 0, 0, 1, 1, 0); + break; + case LED_POWER_BLINKING: + __set_led(0, 0, 1, 1, 1, 1); + break; + } +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + set_led(LED_POWER_BLINKING); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +void check_enetaddr(void) +{ + uchar enetaddr[6]; + + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + /* signal unset/invalid ethaddr to user */ + set_led(LED_INFO_BLINKING); + } +} + +static void erase_environment(void) +{ + struct spi_flash *flash; + + printf("Erasing environment..\n"); + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printf("Erasing flash failed\n"); + return; + } + + spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + spi_flash_free(flash); + do_reset(NULL, 0, 0, NULL); +} + +static void rescue_mode(void) +{ + uchar enetaddr[6]; + + printf("Entering rescue mode..\n"); +#ifdef CONFIG_RANDOM_MACADDR + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + eth_random_enetaddr(enetaddr); + if (eth_setenv_enetaddr("ethaddr", enetaddr)) { + printf("Failed to set ethernet address\n"); + set_led(LED_ALARM_BLINKING); + return; + } + } +#endif + setenv("bootsource", "rescue"); +} + +static void check_push_button(void) +{ + int i = 0; + + while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) { + udelay(100000); + i++; + + if (i == 10) + set_led(LED_INFO_ON); + + if (i >= 100) { + set_led(LED_INFO_BLINKING); + break; + } + } + + if (i >= 100) + erase_environment(); + else if (i >= 10) + rescue_mode(); +} + +int misc_init_r(void) +{ + check_enetaddr(); + check_push_button(); + + return 0; +} +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + if (progress > 0) + return; + + /* this is not an error, eg. bootp with autoload=no will trigger this */ + if (progress == -BOOTSTAGE_ID_NET_LOADED) + return; + + set_led(LED_ALARM_BLINKING); +} +#endif diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h new file mode 100644 index 0000000000..2a2642e487 --- /dev/null +++ b/board/buffalo/lsxl/lsxl.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __LSXL_H +#define __LSXL_H + +#define GPIO_HDD_POWER 10 +#define GPIO_USB_VBUS 11 +#define GPIO_FAN_HIGH 18 +#define GPIO_FAN_LOW 19 +#define GPIO_FUNC_LED 36 +#define GPIO_ALARM_LED 37 +#define GPIO_INFO_LED 38 +#define GPIO_POWER_LED 39 +#define GPIO_FAN_LOCK 40 +#define GPIO_FUNC_BUTTON 41 +#define GPIO_POWER_SWITCH 42 +#define GPIO_POWER_AUTO_SWITCH 43 +#define GPIO_FUNC_RED_LED 48 + +#define _BIT(x) (1<<(x)) + +#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS) \ + | _BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW))) + +#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32))) + +#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS)) + +#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW)) + +#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_BUTTON - 32) \ + | _BIT(GPIO_POWER_SWITCH - 32) \ + | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#endif /* __LSXL_H */ diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index ff3421d576..bac9ce55a8 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -71,7 +71,7 @@ int board_early_init_f(void) MPP49_GPIO, /* LED orange */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 89e6b08e7f..700c184944 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -99,6 +99,39 @@ int board_init(void) return 0; } +static u32 cm_t3x_rev; + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + if (!cm_t3x_rev) + cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + + return cm_t3x_rev; +}; + +/* + * Routine: misc_init_r + * Description: display die ID + */ +int misc_init_r(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); + dieid_num_r(); + + return 0; +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c index dfa171d233..b0af103cdd 100644 --- a/board/cm_t35/eeprom.c +++ b/board/cm_t35/eeprom.c @@ -27,8 +27,7 @@ #define BOARD_SERIAL_OFFSET_LEGACY 8 #define BOARD_REV_OFFSET 0 #define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 4 -#define BOARD_REV_SIZE_LEGACY 2 +#define BOARD_REV_SIZE 2 #define MAC_ADDR_OFFSET 4 #define MAC_ADDR_OFFSET_LEGACY 0 @@ -100,25 +99,32 @@ int cm_t3x_eeprom_read_mac_addr(uchar *buf) } /* - * Routine: get_board_rev - * Description: read system revision + * Routine: cm_t3x_eeprom_get_board_rev + * Description: read system revision from eeprom */ -u32 get_board_rev(void) +u32 cm_t3x_eeprom_get_board_rev(void) { u32 rev = 0; + char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; - int len = BOARD_REV_SIZE_LEGACY; if (eeprom_setup_layout()) return 0; - if (eeprom_layout != LAYOUT_LEGACY) { + if (eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - len = BOARD_REV_SIZE; - } - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, len)) + if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) return 0; + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", rev); + rev = simple_strtoul(str, NULL, 10); + } + return rev; }; diff --git a/board/cm_t35/eeprom.h b/board/cm_t35/eeprom.h index ec772c6710..38824d162b 100644 --- a/board/cm_t35/eeprom.h +++ b/board/cm_t35/eeprom.h @@ -23,11 +23,16 @@ #ifdef CONFIG_DRIVER_OMAP34XX_I2C int cm_t3x_eeprom_read_mac_addr(uchar *buf); +u32 cm_t3x_eeprom_get_board_rev(void); #else static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) { return 1; } +static inline u32 cm_t3x_eeprom_get_board_rev(void) +{ + return 0; +} #endif #endif diff --git a/board/compal/dts/tegra2-paz00.dts b/board/compal/dts/tegra2-paz00.dts new file mode 100644 index 0000000000..9e3e169069 --- /dev/null +++ b/board/compal/dts/tegra2-paz00.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 3b48917430..0c09ce0a46 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -48,15 +48,15 @@ static void pin_mux_mmc(void) pinmux_tristate_disable(PINGRP_GMA); pinmux_tristate_disable(PINGRP_GME); - /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1); + /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDMMC1); + pinmux_tristate_disable(PINGRP_SDIO1); /* For power GPIO PV1 */ pinmux_tristate_disable(PINGRP_UAC); - /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); + /* For CD GPIO PV5 */ + pinmux_tristate_disable(PINGRP_GPV); } /* this is a weak define that we are overriding */ @@ -74,7 +74,7 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ - tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PI5); + tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; } diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts new file mode 100644 index 0000000000..db79e7796d --- /dev/null +++ b/board/compulab/dts/tegra2-trimslice.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile new file mode 100644 index 0000000000..bf624f41a2 --- /dev/null +++ b/board/compulab/trimslice/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../nvidia/common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +COBJS += ../../nvidia/common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c new file mode 100644 index 0000000000..7167c914e0 --- /dev/null +++ b/board/compulab/trimslice/trimslice.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> +#include <asm/gpio.h> +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on TrimSlice - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + + /* For CD GPIO PP1 */ + pinmux_tristate_disable(PINGRP_DAP3); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ + tegra2_mmc_init(0, 4, -1, GPIO_PP1); + + /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ + tegra2_mmc_init(3, 4, -1, -1); + + return 0; +} diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 990d79fe11..11260fe5f6 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, /* thermal sensor */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile index fdd188ecfc..bd2174fec3 100644 --- a/board/efikamx/Makefile +++ b/board/efikamx/Makefile @@ -33,12 +33,11 @@ ifdef CONFIG_CMD_USB COBJS += efikamx-usb.o endif -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 6c0d931eea..0874e9c4e8 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -35,6 +35,8 @@ #include <mmc.h> #include <net.h> #include <netdev.h> +#include <spi.h> +#include <linux/ctype.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/da850_lowlevel.h> @@ -86,16 +88,22 @@ static const struct pinmux_config enbw_pins[] = { { pinmux(5), 1, 0 }, { pinmux(5), 1, 3 }, { pinmux(5), 1, 7 }, - { pinmux(6), 1, 0 }, - { pinmux(6), 1, 1 }, + { pinmux(5), 1, 5 }, + { pinmux(5), 1, 4 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 2 }, + { pinmux(5), 1, 1 }, + { pinmux(5), 1, 0 }, + { pinmux(6), 8, 0 }, + { pinmux(6), 8, 1 }, { pinmux(6), 8, 2 }, { pinmux(6), 8, 3 }, - { pinmux(6), 1, 4 }, + { pinmux(6), 8, 4 }, { pinmux(6), 8, 5 }, { pinmux(6), 1, 7 }, { pinmux(7), 8, 2 }, { pinmux(7), 1, 3 }, - { pinmux(7), 1, 6 }, + { pinmux(7), 8, 6 }, { pinmux(7), 1, 7 }, { pinmux(13), 8, 2 }, { pinmux(13), 8, 3 }, @@ -163,24 +171,37 @@ struct gpio_config { unsigned char value; }; -static const struct gpio_config enbw_gpio_config[] = { +static const struct gpio_config enbw_gpio_config_hut[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 1 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 1 }, +}; + +static const struct gpio_config enbw_gpio_config_w[] = { { "RS485 enable", 8, 11, 1, 0 }, { "RS485 iso", 8, 10, 1, 0 }, { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, { "W2HUT RS485 iso", 8, 8, 1, 0 }, +}; + +static const struct gpio_config enbw_gpio_config[] = { { "LAN reset", 7, 15, 1, 1 }, { "ena 11V PLC", 7, 14, 1, 0 }, { "ena 1.5V PLC", 7, 13, 1, 0 }, { "disable VBUS", 7, 12, 1, 1 }, - { "PLC reset", 6, 13, 1, 1 }, + { "PLC reset", 6, 13, 1, 0 }, { "LCM RS", 6, 12, 1, 0 }, { "LCM R/W", 6, 11, 1, 0 }, { "PLC pairing", 6, 10, 1, 1 }, { "PLC MDIO CLK", 6, 9, 1, 0 }, { "HK218", 6, 8, 1, 0 }, { "HK218 Rx", 6, 1, 1, 1 }, - { "TPM reset", 6, 0, 1, 1 }, - { "LCM E", 2, 2, 1, 1 }, + { "TPM reset", 6, 0, 1, 0 }, + { "Board-Type", 3, 9, 0, 0 }, + { "HW-ID0", 2, 7, 0, 0 }, + { "HW-ID1", 2, 6, 0, 0 }, + { "HW-ID2", 2, 3, 0, 0 }, { "PV-IF RxD ena", 0, 15, 1, 1 }, { "LED1", 1, 15, 1, 1 }, { "LED2", 0, 1, 1, 1 }, @@ -229,34 +250,57 @@ static void enbw_cmc_switch(int port, int on) } } -int board_init(void) +static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz) { int i, ret; -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - /* address of boot parameters, not used as booting with DTT */ - gd->bd->bi_boot_params = 0; + for (i = 0; i < sz; i++) { + int gpio = conf[i].bank * 16 + + conf[i].gpio; - for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { - int gpio = enbw_gpio_config[i].bank * 16 + - enbw_gpio_config[i].gpio; - - ret = gpio_request(gpio, enbw_gpio_config[i].name); + ret = gpio_request(gpio, conf[i].name); if (ret) { printf("%s: Could not get %s gpio\n", __func__, - enbw_gpio_config[i].name); - return -1; + conf[i].name); + return ret; } - if (enbw_gpio_config[i].out) + if (conf[i].out) gpio_direction_output(gpio, - enbw_gpio_config[i].value); + conf[i].value); else gpio_direction_input(gpio); } + return 0; +} + +int board_init(void) +{ + int board_type, hw_id; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config)); + + /* detect HW version */ + board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE); + hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2); + printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"), + hw_id); + if (board_type) + enbw_cmc_init_gpio(enbw_gpio_config_w, + ARRAY_SIZE(enbw_gpio_config_w)); + else + enbw_cmc_init_gpio(enbw_gpio_config_hut, + ARRAY_SIZE(enbw_gpio_config_hut)); + /* setup the SUSPSRC for ARM to control emulation suspend */ clrbits_le32(&davinci_syscfg_regs->suspsrc, (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | @@ -267,14 +311,231 @@ int board_init(void) } #ifdef CONFIG_DRIVER_TI_EMAC + +#define KSZ_CMD_READ 0x03 +#define KSZ_CMD_WRITE 0x02 +#define KSZ_ID 0x95 + +static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[2]; + + cmd[0] = KSZ_CMD_READ; + cmd[1] = reg; + cmd_len = 2; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + flags |= SPI_XFER_END; + *val = 0; + cmd_len = 1; + ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags); + if (ret) { + debug("Failed to read (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + return 0; +} + +static int enbw_cmc_switch_read_ident(struct spi_slave *spi) +{ + int ret; + u8 val; + + ret = enbw_cmc_switch_read(spi, 0, &val); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + + if (val != KSZ_ID) + return -EINVAL; + + return 0; +} + +static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg, + unsigned long val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[3]; + + cmd[0] = KSZ_CMD_WRITE; + cmd[1] = reg; + cmd[2] = val; + cmd_len = 3; + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + udelay(1000); + ret = enbw_cmc_switch_read(spi, reg, &cmd[0]); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + if (val != cmd[0]) + debug("warning: reg: %lx va: %x soll: %lx\n", + reg, cmd[0], val); + + return 0; +} + +static int enbw_cmc_eof(unsigned char *ptr) +{ + if (*ptr == 0xff) + return 1; + + return 0; +} + +static char *enbw_cmc_getnewline(char *ptr) +{ + while (*ptr != 0x0a) { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + + ptr++; + return ptr; +} + +static char *enbw_cmc_getvalue(char *ptr, int *value) +{ + int end = 0; + + *value = -EINVAL; + + if (!isxdigit(*ptr)) + end = 1; + + while (end) { + if ((*ptr == '#') || (*ptr == ';')) { + ptr = enbw_cmc_getnewline(ptr); + return ptr; + } + if (ptr != NULL) { + if (isxdigit(*ptr)) { + end = 0; + } else if (*ptr == 0x0a) { + ptr++; + return ptr; + } else { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + } else { + return NULL; + } + } + *value = (int)simple_strtoul((const char *)ptr, &ptr, 16); + ptr++; + return ptr; +} + +static int enbw_cmc_config_switch(unsigned long addr) +{ + struct spi_slave *spi; + char *ptr = (char *)addr; + int value, reg; + int ret; + int bus, cs, max_hz, spi_mode; + + debug("configure switch with file on addr: 0x%lx\n", addr); + + bus = 0; + cs = 0; + max_hz = 1000000; + spi_mode = 0; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printf("Failed to set up slave\n"); + return -EINVAL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + ret = enbw_cmc_switch_read_ident(spi); + if (ret) + goto err_claim_bus; + + ptr = (char *)addr; + while (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, ®); + if (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, &value); + if ((ptr != NULL) && (value >= 0)) + if (enbw_cmc_switch_write(spi, reg, value)) + goto err_read; + } + } + return 0; + +err_read: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return -EINVAL; +} + +static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long addr; + + if (argc < 2) + return cmd_usage(cmdtp); + + addr = simple_strtoul(argv[1], NULL, 16); + enbw_cmc_config_switch(addr); + + return 0; +} + +U_BOOT_CMD(switch, 3, 1, do_switch, + "switch addr", + "[addr]" +); + /* * Initializes on-board ethernet controllers. */ int board_eth_init(bd_t *bis) { -#ifdef CONFIG_DRIVER_TI_EMAC + const char *s; + size_t len; + davinci_emac_mii_mode_sel(0); -#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* send a config file to the switch */ + s = hwconfig_subarg("switch", "config", &len); + if (len) { + unsigned long addr = simple_strtoul(s, NULL, 16); + + enbw_cmc_config_switch(addr); + } if (!davinci_emac_initialize()) { printf("Error: Ethernet init failed!\n"); @@ -546,6 +807,29 @@ ulong bootcount_load(void) } #endif +ulong post_word_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + return in_be32(®->scratch2); +} + +void post_word_store(ulong value) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + writel(RTC_KICK0R_WE, ®->kick0r); + writel(RTC_KICK1R_WE, ®->kick1r); + out_be32(®->scratch2, value); +} + void board_gpio_init(void) { struct davinci_gpio *gpio = davinci_gpio_bank01; @@ -558,6 +842,19 @@ void board_gpio_init(void) clrbits_le32(&gpio->out_data, 0x8000407e); /* set LED 1 - 5 to state on */ setbits_le32(&gpio->out_data, 0x8000001e); + + /* + * set some gpio pins to low, this is needed early, + * so we have no gpio Interface here + * gpios: + * 8[8] Mode PV select low + * 8[9] Debug Rx Enable low + * 8[10] Mode Select PV low + * 8[11] Counter Interface RS485 Rx-Enable low + */ + gpio = davinci_gpio_bank8; + clrbits_le32(&gpio->dir, 0x00000f00); + clrbits_le32(&gpio->out_data, 0x0f00); } int board_late_init(void) diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile index f3b13bccaf..ab18944f49 100644 --- a/board/esg/ima3-mx53/Makefile +++ b/board/esg/ima3-mx53/Makefile @@ -25,7 +25,7 @@ LIB = $(obj)lib$(BOARD).o COBJS := ima3-mx53.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 6587c454fe..00cc0cc2fa 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -161,6 +161,20 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), }; +#define HW_DRAM_CTL29 (0x74 >> 2) +#define CS_MAP 0xf +#define COLUMN_SIZE 0x2 +#define ADDR_PINS 0x1 +#define APREBIT 0xa + +#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ + ADDR_PINS << 8 | APREBIT) + +void mx28_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; +} + void board_init_ll(void) { mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index 470588eb66..224eaa3c73 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx51evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile index eac4b2a903..335af11790 100644 --- a/board/freescale/mx53ard/Makefile +++ b/board/freescale/mx53ard/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53ard.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile index b7f92b3d87..dcc83e2d51 100644 --- a/board/freescale/mx53evk/Makefile +++ b/board/freescale/mx53evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index a6ea9396fb..8bc69a92c1 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -24,12 +24,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53loco.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d8e027ce66..cbdcfadf27 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -75,6 +75,9 @@ u32 get_board_rev(void) int rev = readl(&fuse->gp[6]); + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + rev = 0; + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } @@ -495,11 +498,6 @@ int print_cpuinfo(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - setup_iomux_i2c(); - if (!power_init()) - clock_1GHz(); - print_cpuinfo(); - setenv("stdout", "serial"); return 0; @@ -511,6 +509,10 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; mxc_set_sata_internal_clock(); + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); + print_cpuinfo(); lcd_enable(); diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile index ed8e473649..8a404c8ab7 100644 --- a/board/freescale/mx53smd/Makefile +++ b/board/freescale/mx53smd/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53smd.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile index 79bc315dd3..6ce449552a 100644 --- a/board/freescale/mx6qarm2/Makefile +++ b/board/freescale/mx6qarm2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qarm2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index ceecbf925d..bf941a3198 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile index 53c26e7ba6..cf344e4323 100644 --- a/board/freescale/mx6qsabrelite/Makefile +++ b/board/freescale/mx6qsabrelite/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qsabrelite.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index c389427191..62498abca3 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/spear/spear300/config.mk b/board/karo/tk71/Makefile index 5848ef89f8..934e3911d1 100644 --- a/board/spear/spear300/config.mk +++ b/board/karo/tk71/Makefile @@ -1,6 +1,7 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# Copyright (C) 2012 Marek Vasut <marex@denx.de> +# on behalf of DENX Software Engineering GmbH +# # # See file CREDITS for list of people who contributed to this # project. @@ -12,28 +13,33 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA # -######################################################################### +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tk71.o -CONFIG_SYS_TEXT_BASE = 0x00700000 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -ALL-y += $(obj)u-boot.img +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg new file mode 100644 index 0000000000..0166826e72 --- /dev/null +++ b/board/karo/tk71/kwbimage.cfg @@ -0,0 +1,174 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# adopted to TK71 by +# Nils Faerber <nils.faerber@kernelconcepts.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c new file mode 100644 index 0000000000..96410d77d6 --- /dev/null +++ b/board/karo/tk71/tk71.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TK71_OE_LOW (~0) +#define TK71_OE_HIGH (~0) +#define TK71_OE_VAL_LOW (0) +#define TK71_OE_VAL_HIGH (0) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET + +#define MV88E1116_MAC_CTRL2_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +static void mv_phy_88e1118_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1118 Initialized on %s\n", name); +} + +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* configure and initialize PHY */ + mv_phy_88e1118_init("egiga0"); + +} +#endif diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index f457aa30c6..aab706e6c9 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -131,6 +131,11 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void); +int trigger_fpga_config(void); +int wait_for_fpga_config(void); +int fpga_reset(void); +int toggle_eeprom_spi_bus(void); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index aa51255265..13d485aedb 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o ../common/common.o ../common/ivm.o +ifdef CONFIG_KM_FPGA_CONFIG +COBJS += fpga_config.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c new file mode 100644 index 0000000000..fcc5fe6c65 --- /dev/null +++ b/board/keymile/km_arm/fpga_config.c @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> + +/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ +#define KM_XLX_PROGRAM_B_PIN 39 + +#define BOCO_ADDR 0x10 + +#define ID_REG 0x00 +#define BOCO2_ID 0x5b + +static int check_boco2(void) +{ + int ret; + u8 id; + + ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); + if (ret) { + printf("%s: error reading the BOCO id !!\n", __func__); + return ret; + } + + return (id == BOCO2_ID); +} + +static int boco_clear_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval &= ~flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int boco_set_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval |= flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +#define SPI_REG 0x06 +#define CFG_EEPROM 0x02 +#define FPGA_PROG 0x04 +#define FPGA_INIT_B 0x10 +#define FPGA_DONE 0x20 + +static int fpga_done(void) +{ + int ret = 0; + u8 regval; + + /* this is only supported with the boco2 design */ + if (!check_boco2()) + return 0; + + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, SPI_REG); + return 0; + } + + return regval & FPGA_DONE ? 1 : 0; +} + +int skip; + +int trigger_fpga_config(void) +{ + int ret = 0; + + /* if the FPGA is already configured, we do not want to + * reconfigure it */ + skip = 0; + if (fpga_done()) { + printf("PCIe FPGA config: skipped\n"); + skip = 1; + return 0; + } + + if (check_boco2()) { + /* we have a BOCO2, this has to be triggered here */ + + /* make sure the FPGA_can access the EEPROM */ + ret = boco_clear_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + /* trigger the config start */ + ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + /* up signal for pulse end */ + ret = boco_set_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + /* finally, raise INIT_B to remove the config delay */ + ret = boco_set_bits(SPI_REG, FPGA_INIT_B); + if (ret) + return ret; + + } else { + /* we do it the old way, with the gpio pin */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + /* small delay for the pulse */ + udelay(10); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + } + + return 0; +} + +int wait_for_fpga_config(void) +{ + int ret = 0; + u8 spictrl; + u32 timeout = 20000; + + if (skip) + return 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe FPGA config:"); + do { + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); + if (ret) { + printf("%s: error reading the BOCO spictrl !!\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + return -EFAULT; + } + udelay(10); + } while (!(spictrl & FPGA_DONE)); + + printf(" done\n"); + + return 0; +} + +#define PRST1 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04 + +int fpga_reset(void) +{ + int ret = 0; + u8 resets; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + ret = boco_set_bits(PRST1, resets); + if (ret) + return ret; + + return 0; +} + +/* the FPGA was configured, we configure the BOCO2 so that the EEPROM + * is available from the Bobcat SPI bus */ +int toggle_eeprom_spi_bus(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_set_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + return 0; +} + diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9e9940c51f..2b2ca39376 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -33,6 +33,7 @@ #include <nand.h> #include <netdev.h> #include <miiphy.h> +#include <spi.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> @@ -113,7 +114,7 @@ u32 kwmpp_config[] = { 0 }; -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -133,10 +134,10 @@ int startup_allowed(void) } #endif -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { @@ -201,7 +202,7 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -242,90 +243,93 @@ int misc_init_r(void) int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp; - kirkwood_mpp_conf(kwmpp_config); + /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ /* - * The FLASH_GPIO_PIN switches between using a + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + /* + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); #if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ + /* + * Reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f + */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + +#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); #endif + return 0; } -int board_init(void) +int board_late_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; +#if defined(CONFIG_KMCOGE5UN) +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); + + /* if pin 1 do full erase */ + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } +#endif +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif return 0; } -#if defined(CONFIG_CMD_SF) -int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int board_spi_claim_bus(struct spi_slave *slave) { - u32 tmp; - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "off") == 0)) { - printf("SPI FLASH disabled, NAND enabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - } else if ((strcmp(argv[1], "on") == 0)) { - printf("SPI FLASH enabled, NAND disabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); - } else { - return cmd_usage(cmdtp); - } + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); return 0; } -U_BOOT_CMD( - spitoggle, 2, 0, do_spi_toggle, - "En-/disable SPI FLASH access", - "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" - ); -#endif +void board_spi_release_bus(struct spi_slave *slave) +{ + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); +} int dram_init(void) { @@ -347,15 +351,15 @@ void dram_init_banksize(void) } } -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)) -#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1) /* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -367,15 +371,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ @@ -410,7 +414,7 @@ const ulong patterns[] = { 0x00000000, 0xFF00FF00, 0x0F0F0F0F, 0xF0F0F0F0}; -const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); +const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns); const ulong OFFS_PATTERN = 3; const ulong REPEAT_PATTERN = 1000; @@ -486,7 +490,11 @@ int get_scl(void) int post_hotkeys_pressed(void) { +#if defined(CONFIG_KM_COGE5UN) + return kw_gpio_get_value(KM_POST_EN_L); +#else return !kw_gpio_get_value(KM_POST_EN_L); +#endif } ulong post_word_load(void) diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 2faaf2b4c9..6df2ad7902 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F # DDR Controller Control High DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low # bit3-0 : 0000, required # bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read +# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read # bit15-12: 0100, internal ODT assertion 4 cycles after read # bit19-16: 1000, internal ODT de-assertion 8 cycles after read # bit31-20: 0 , required diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg new file mode 100644 index 0000000000..bcce9073f6 --- /dev/null +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15] + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay + +DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) + +DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg new file mode 100644 index 0000000000..3e1237bbe3 --- /dev/null +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles + +DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 23aa0b9d19..307937a836 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -21,12 +21,11 @@ */ #include <common.h> -#include <ns16550.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart-spi-switch.h> #include <asm/arch/tegra2.h> -#include <asm/arch/tegra2_spi.h> +#include <asm/arch/tegra_spi.h> /* position of the UART/SPI select switch */ @@ -40,7 +39,6 @@ enum spi_uart_switch { /* Information about the spi/uart switch */ struct spi_uart { int gpio; /* GPIO to control switch */ - NS16550_t regs; /* Address of UART affected */ u32 port; /* Port number of UART affected */ }; @@ -52,7 +50,6 @@ static void get_config(struct spi_uart *config) { #if defined CONFIG_SPI_CORRUPTS_UART config->gpio = CONFIG_UART_DISABLE_GPIO; - config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART; config->port = CONFIG_SPI_CORRUPTS_UART_NR; #else config->gpio = -1; @@ -101,34 +98,24 @@ static void spi_uart_switch(struct spi_uart *config, if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) return; - /* if the UART was selected, allow it to drain */ - if (switch_pos == SWITCH_UART) - NS16550_drain(config->regs, config->port); + /* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */ + udelay(CONFIG_SPI_CORRUPTS_UART_DLY); /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); /* - * On Seaboard, MOSI/MISO are shared w/UART. - * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. - * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. - */ + * On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); switch_pos = new_pos; - - /* if the SPI was selected, clear any junk bytes in the UART */ - if (switch_pos == SWITCH_UART) { - /* TODO: What if it is part-way through clocking in junk? */ - udelay(100); - NS16550_clear(config->regs, config->port); - } } -void pinmux_select_uart(NS16550_t regs) +void pinmux_select_uart(void) { - /* Also prevents calling spi_uart_switch() before relocation */ - if (regs == local.regs) spi_uart_switch(&local, SWITCH_UART); } diff --git a/board/nvidia/dts/tegra2-harmony.dts b/board/nvidia/dts/tegra2-harmony.dts new file mode 100644 index 0000000000..4f60a05f33 --- /dev/null +++ b/board/nvidia/dts/tegra2-harmony.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/dts/tegra2-ventana.dts b/board/nvidia/dts/tegra2-ventana.dts new file mode 100644 index 0000000000..900e871d74 --- /dev/null +++ b/board/nvidia/dts/tegra2-ventana.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/dts/tegra2-whistler.dts b/board/nvidia/dts/tegra2-whistler.dts new file mode 100644 index 0000000000..b22d4073f6 --- /dev/null +++ b/board/nvidia/dts/tegra2-whistler.dts @@ -0,0 +1,67 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; + + aliases { + i2c0 = "/i2c@7000d000"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x20000000 >; + }; + + clocks { + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + + pmic@3c { + compatible = "maxim,max8907b"; + reg = <0x3c>; + + clk_32k: clock { + compatible = "fixed-clock"; + /* + * leave out for now due to CPP: + * #clock-cells = <0>; + */ + clock-frequency = <32768>; + }; + }; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 8f8e7bf3fe..f27ad37b70 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -29,7 +29,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif @@ -41,7 +41,7 @@ void gpio_config_uart(void) { } -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 94efb1e83d..36039c4ed8 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -29,7 +29,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif @@ -54,7 +54,7 @@ void gpio_config_uart(void) } #endif -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile new file mode 100644 index 0000000000..a910577f21 --- /dev/null +++ b/board/nvidia/whistler/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c new file mode 100644 index 0000000000..3ec24df2e7 --- /dev/null +++ b/board/nvidia/whistler/whistler.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> +#include <asm/gpio.h> +#ifdef CONFIG_TEGRA_MMC +#include <mmc.h> +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on Whistler - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + uchar val; + int ret; + + debug("board_mmc_init called\n"); + + /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x29; + ret = i2c_write(0x3c, 0x46, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); + val = 0x00; + ret = i2c_write(0x3c, 0x45, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); + val = 0x1f; + ret = i2c_write(0x3c, 0x44, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ + tegra2_mmc_init(0, 8, -1, -1); + + /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ + tegra2_mmc_init(1, 8, -1, -1); + + return 0; +} + +/* this is a weak define that we are overriding */ +void pin_mux_usb(void) +{ + uchar val; + int ret; + + /* + * This is a hack. This should be represented in DT using the + * vbus-gpio property. However, U-Boot's DT support doesn't + * support any GPIO controller other than the Tegra's yet. + */ + + /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x03; + ret = i2c_write(0x20, 2, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 2 failed: %d\n", ret); + val = 0xfc; + ret = i2c_write(0x20, 6, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 6 failed: %d\n", ret); +} diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 65f2c2ea6a..1164d6bf3f 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -66,7 +66,7 @@ int board_early_init_f(void) MPP29_GPIO, /* USB Copy button */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 32786e228f..3b078da65d 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,81 +26,16 @@ #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> DECLARE_GLOBAL_DATA_PTR; -struct exynos5_gpio_part1 *gpio1; #ifdef CONFIG_SMC911X -static void smc9115_pre_init(void) +static int smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); - } + int err; /* Ethernet needs data bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK) @@ -112,14 +47,20 @@ static void smc9115_pre_init(void) | SROMC_BC_PMC(0x01); /* Select and configure the SROMC bank */ + err = exynos_pinmux_config(PERIPH_ID_SROMC, + CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT); + if (err) { + debug("SROMC not configured\n"); + return err; + } + s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + return 0; } #endif int board_init(void) { - gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } @@ -168,7 +109,8 @@ void dram_init_banksize(void) int board_eth_init(bd_t *bis) { #ifdef CONFIG_SMC911X - smc9115_pre_init(); + if (smc9115_pre_init()) + return -1; return smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif return 0; @@ -186,31 +128,12 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPC2[0] SD_2_CLK(2) - * GPC2[1] SD_2_CMD(2) - * GPC2[2] SD_2_CDn - * GPC2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPC2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X); + int err; - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; } err = s5p_mmc_init(2, 4); @@ -218,63 +141,40 @@ int board_mmc_init(bd_t *bis) } #endif -static void board_uart_init(void) +static int board_uart_init(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - int i; + int err; - /* - * UART0 GPIOs : GPA0CON[3:0] 0x2222 - * Must set CFG17 switches to select UART0 to use. - */ - for (i = 0; i <= 3; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); + if (err) { + debug("UART0 not configured\n"); + return err; } - /* - * UART1 GPIOs : GPA0CON[5:4] 0x22 - * Must set CFG17 switches to select UART1 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); + if (err) { + debug("UART1 not configured\n"); + return err; } - /* - * UART2 GPIOs : GPA1CON[1:0] 0x22 - * Must set CFG17 switches to select UART2 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 0; i <= 1; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); + if (err) { + debug("UART2 not configured\n"); + return err; } - /* - * UART3 GPIOs : GPA1CON[5:4] 0x22 - * Must set CFG16 switches to select UART3 to use. - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + if (err) { + debug("UART3 not configured\n"); + return err; } - /* - * There's no mux for UART4--it's internal only - */ + return 0; } #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - board_uart_init(); - return 0; + return board_uart_init(); } #endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a0eec75bc5..a8b2b11c4c 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -220,6 +220,7 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; + u32 val = 0; struct pmic *p = get_pmic(); if (pmic_probe(p)) @@ -228,11 +229,17 @@ static int s5pc210_phy_control(int on) if (on) { ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_ON); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); } else { - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_OFF); } @@ -461,42 +468,44 @@ static int mipi_power(void) return 0; } +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 720, + .vl_row = 1280, + .vl_width = 720, + .vl_height = 1280, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ + + /* s6e8ax0 Panel infomation */ + .vl_hspw = 5, + .vl_hbpd = 10, + .vl_hfpd = 10, + + .vl_vspw = 2, + .vl_vbpd = 1, + .vl_vfpd = 13, + .vl_cmd_allow_len = 0xf, + + .win_id = 3, + .cfg_gpio = NULL, + .backlight_on = NULL, + .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ + .reset_lcd = lcd_reset, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 0, + .reset_delay = 0, + .interface_mode = FIMD_RGB_INTERFACE, + .mipi_enabled = 1, +}; + void init_panel_info(vidinfo_t *vid) { - vid->vl_freq = 60; - vid->vl_col = 720; - vid->vl_row = 1280; - vid->vl_width = 720; - vid->vl_height = 1280; - vid->vl_clkp = CONFIG_SYS_HIGH; - vid->vl_hsp = CONFIG_SYS_LOW; - vid->vl_vsp = CONFIG_SYS_LOW; - vid->vl_dp = CONFIG_SYS_LOW; - - vid->vl_bpix = 5; - vid->dual_lcd_enabled = 0; - - /* s6e8ax0 Panel */ - vid->vl_hspw = 5; - vid->vl_hbpd = 10; - vid->vl_hfpd = 10; - - vid->vl_vspw = 2; - vid->vl_vbpd = 1; - vid->vl_vfpd = 13; - vid->vl_cmd_allow_len = 0xf; - - vid->win_id = 3; - vid->cfg_gpio = NULL; - vid->backlight_on = NULL; - vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ - vid->reset_lcd = lcd_reset; - - vid->init_delay = 0; - vid->power_on_delay = 0; - vid->reset_delay = 0; - vid->interface_mode = FIMD_RGB_INTERFACE; - vid->mipi_enabled = 1; vid->logo_on = 1, vid->resolution = HD_RESOLUTION, vid->rgb_mode = MODE_RGB_P, diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 11f81e4803..5c66c3f092 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,10 @@ endif LIB = $(obj)lib$(VENDOR).o +ifndef CONFIG_SPL_BUILD COBJS := spr_misc.o SOBJS := spr_lowlevel_init.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 0812c20b8c..99a6595966 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -25,10 +25,10 @@ #include <command.h> #include <i2c.h> #include <net.h> +#include <linux/mtd/st_smi.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_emi.h> -#include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h> #define CPU 0 @@ -36,31 +36,16 @@ #define SRAM_REL 0xD2801000 DECLARE_GLOBAL_DATA_PTR; -static struct chip_data chip_data; + +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer); +#endif int dram_init(void) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_1 *table_1_1; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - + /* Store complete RAM size and return */ gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); - if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { - table_1_1 = &xloader_tb->table.table_1_1; - chip->dramfreq = table_1_1->ddrfreq; - chip->dramtype = table_1_1->ddrtype; - - } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - chip->dramfreq = table_1_2->ddrfreq; - chip->dramtype = table_1_2->ddrtype; - } else { - chip->dramfreq = -1; - } - return 0; } @@ -70,6 +55,13 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = gd->ram_size; } +int board_early_init_f() +{ +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} int misc_init_r(void) { #if defined(CONFIG_CMD_NET) @@ -84,6 +76,10 @@ int misc_init_r(void) setenv("stdin", "usbtty"); setenv("stdout", "usbtty"); setenv("stderr", "usbtty"); + +#ifndef CONFIG_SYS_NO_DCACHE + dcache_enable(); +#endif #endif return 0; } @@ -145,31 +141,18 @@ void spear_emi_init(void) int spear_board_init(ulong mach_type) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - gd->bd->bi_arch_number = mach_type; /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; - /* CPU is initialized to work at 333MHz in Xloader */ - chip->cpufreq = 333; - - if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - memcpy(chip->version, table_1_2->version, - sizeof(chip->version)); - } - #ifdef CONFIG_SPEAR_EMI spear_emi_init(); #endif return 0; } +#if defined(CONFIG_CMD_NET) static int i2c_read_mac(uchar *buffer) { u8 buf[2]; @@ -206,18 +189,18 @@ static int write_mac(uchar *mac) return 0; } - puts("I2C EEPROM writing failed \n"); + puts("I2C EEPROM writing failed\n"); return -1; } +#endif int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); - struct chip_data *chip = &chip_data; + unsigned int frequency; +#if defined(CONFIG_CMD_NET) unsigned char mac[6]; - unsigned int reg, frequency; - char *s, *e; - char i2c_mac[20]; +#endif if ((argc > 3) || (argc < 2)) return cmd_usage(cmdtp); @@ -236,19 +219,18 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!strcmp(argv[1], "cpufreq")) { sram_setfreq(CPU, frequency); printf("CPU frequency changed to %u\n", frequency); - - chip->cpufreq = frequency; } else { sram_setfreq(DDR, frequency); printf("DDR frequency changed to %u\n", frequency); - - chip->dramfreq = frequency; } return 0; + +#if defined(CONFIG_CMD_NET) } else if (!strcmp(argv[1], "ethaddr")) { - s = argv[2]; + u32 reg; + char *e, *s = argv[2]; for (reg = 0; reg < 6; ++reg) { mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; if (s) @@ -257,34 +239,15 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) write_mac(mac); return 0; +#endif } else if (!strcmp(argv[1], "print")) { - - if (chip->cpufreq == -1) - printf("CPU Freq = Not Known\n"); - else - printf("CPU Freq = %d MHz\n", chip->cpufreq); - - if (chip->dramfreq == -1) - printf("DDR Freq = Not Known\n"); - else - printf("DDR Freq = %d MHz\n", chip->dramfreq); - - if (chip->dramtype == DDRMOBILE) - printf("DDR Type = MOBILE\n"); - else if (chip->dramtype == DDR2) - printf("DDR Type = DDR2\n"); - else - printf("DDR Type = Not Known\n"); - +#if defined(CONFIG_CMD_NET) if (!i2c_read_mac(mac)) { - sprintf(i2c_mac, "%pM", mac); - printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + printf("Ethaddr (from i2c mem) = %pM\n", mac); } else { printf("Ethaddr (from i2c mem) = Not set\n"); } - - printf("Xloader Rev = %s\n", chip->version); - +#endif return 0; } @@ -294,4 +257,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(chip_config, 3, 1, do_chip_config, "configure chip", "chip_config cpufreq/ddrfreq frequency\n" +#if defined(CONFIG_CMD_NET) + "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" +#endif "chip_config print"); diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 60ee54470e..f809c2dc91 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -22,12 +22,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,18 +45,33 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 03dfe16175..8609a5910f 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -23,12 +23,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -42,18 +46,50 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; + + if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, + CONFIG_MACB1_PHY) >= 0) + ret++; + + if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, + CONFIG_MACB2_PHY) >= 0) + ret++; - return -1; + if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, + CONFIG_MACB3_PHY) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 2ba2dbb566..54a2e1003c 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -23,15 +23,29 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +#define PLGPIO_SEL_36 0xb3000028 +#define PLGPIO_IO_36 0xb3000038 + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +static void spear_phy_reset(void) +{ + writel(0x10, PLGPIO_IO_36); + writel(0x10, PLGPIO_SEL_36); +} int board_init(void) { + spear_phy_reset(); return spear_board_init(MACH_TYPE_SPEAR320); } @@ -42,18 +56,39 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile index e2bd5ab7f5..ee66fc6520 100644 --- a/board/spear/spear600/Makefile +++ b/board/spear/spear600/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := spear600.o +endif SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk deleted file mode 100644 index 5848ef89f8..0000000000 --- a/board/spear/spear600/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -CONFIG_SYS_TEXT_BASE = 0x00700000 - -ALL-y += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index eef9a3771c..814f9ccb6b 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -22,12 +22,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,13 +45,31 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); + fsmc_nand_init(nand); +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; +#if defined(CONFIG_DW_AUTONEG) + interface = PHY_INTERFACE_MODE_GMII; +#endif + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif + return ret; } diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c index 13dc60361a..5e2d53ab42 100644 --- a/board/ti/am335x/evm.c +++ b/board/ti/am335x/evm.c @@ -29,17 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; /* * Basic board specific setup */ -int init_basic_setup(void) -{ - /* Initialize the Timer */ - init_timer(); - - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; - - return 0; -} - int board_init(void) { enable_uart0_pin_mux(); @@ -49,7 +38,7 @@ int board_init(void) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - init_basic_setup(); + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; return 0; } diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index 296eb682e1..a82795dc13 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -47,6 +47,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ + {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ + {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ + {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ + {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ }; @@ -114,10 +123,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ - {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ - {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ - {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ @@ -254,11 +259,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ - {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ - {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ - {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ - {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 6140b999ef..0760dad620 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -53,8 +53,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ - +{UART3_TX_IRTX, (M0)}, /* uart3_tx */ +{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ +{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ +{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { @@ -135,14 +145,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ - {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ @@ -210,9 +212,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile index 393ad68f77..1e018b0701 100644 --- a/board/ttcontrol/vision2/Makefile +++ b/board/ttcontrol/vision2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := vision2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### |