powerpc: Remove P1022DS_36BIT_NAND_defconfig board

DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Timur Tabi <timur@tabi.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

11 files changed, 0 insertions, 1342 deletions

diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig
deleted file mode 100644
index f1792de8e3..0000000000
--- a/board/freescale/p1022ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1022DS
-
-config SYS_BOARD
-	default "p1022ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P1022DS"
-
-endif
diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS
deleted file mode 100644
index 62256c3703..0000000000
--- a/board/freescale/p1022ds/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-P1022DS BOARD
-M:	Timur Tabi <timur@tabi.org>
-S:	Maintained
-F:	board/freescale/p1022ds/
-F:	include/configs/P1022DS.h
-F:	configs/P1022DS_defconfig
-F:	configs/P1022DS_36BIT_defconfig
-F:	configs/P1022DS_36BIT_NAND_defconfig
-F:	configs/P1022DS_36BIT_SDCARD_defconfig
-F:	configs/P1022DS_36BIT_SPIFLASH_defconfig
-F:	configs/P1022DS_NAND_defconfig
-F:	configs/P1022DS_SDCARD_defconfig
-F:	configs/P1022DS_SPIFLASH_defconfig
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
deleted file mode 100644
index 699e5b5288..0000000000
--- a/board/freescale/p1022ds/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2010 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-endif
-obj-y	+= p1022ds.o
-obj-y	+= ddr.o
-obj-$(CONFIG_FSL_DIU_FB) += diu.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README
deleted file mode 100644
index 04d9197074..0000000000
--- a/board/freescale/p1022ds/README
+++ /dev/null
@@ -1,23 +0,0 @@
-Overview
---------
-P1022ds is a Low End Dual core platform supporting the P1022 processor
-of QorIQ series. P1022 is an e500 based dual core SOC.
-
-
-Pin Multiplex(hwconfig setting)
--------------------------------
-Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
-via hwconfig, i.e:
-'setenv hwconfig usb2' to enable USB2 and disable eTsec2
-'setenv hwconfig tdm' to enable TDM and disable Audio
-'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
- and disable TDM
-'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
-'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
- is 11MHz), disable eTsec2 and TDM
-
-Warning: TDM and AUDIO can not enable simultaneous !
-and AUDIO codec clock sources only setting as 11MHz or 12MHz !
-'setenv hwconfig 'audclk:12;tdm'	--- error !
-'setenv hwconfig 'audclk:11;tdm'	--- error !
-'setenv hwconfig 'audclk:10'		--- error !
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
deleted file mode 100644
index 70932115f4..0000000000
--- a/board/freescale/p1022ds/ddr.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;		/* Range: 0-8 */
-	u32 cpo;		/* Range: 2-31 */
-	u32 write_data_delay;	/* Range: 0-6 */
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters dimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{1,  549,    5,  31,     3, 0},
-	{1,  850,    5,  31,     5, 0},
-	{2,  549,    5,  31,     3, 0},
-	{2,  850,    5,  31,     5, 0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned long ddr_freq;
-	unsigned int i;
-
-
-	if (ctrl_num) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	/* set odt_rd_cfg and odt_wr_cfg. */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = 0;
-		popts->cs_local_opts[i].odt_wr_cfg = 1;
-	}
-
-	pbsp = dimm0;
-	/*
-	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp->clk_adjust;
-		popts->cpo_override = pbsp->cpo;
-		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twot_en = pbsp->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	popts->half_strength_driver_enable = 1;
-
-	/* Per AN4039, enable ZQ calibration. */
-	popts->zq_en = 1;
-
-	/*
-	 * For wake-up on ARP, we need auto self refresh enabled
-	 */
-	popts->auto_self_refresh_en = 1;
-	popts->sr_it = 0xb;
-}
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
deleted file mode 100644
index 918b4b9f6a..0000000000
--- a/board/freescale/p1022ds/diu.c
+++ /dev/null
@@ -1,478 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Authors: Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include "../common/ngpixis.h"
-#include <fsl_diu_fb.h>
-
-/* The CTL register is called 'csr' in the ngpixis_t structure */
-#define PX_CTL_ALTACC		0x80
-
-#define PX_BRDCFG0_ELBC_SPI_MASK	0xc0
-#define PX_BRDCFG0_ELBC_SPI_ELBC	0x00
-#define PX_BRDCFG0_ELBC_SPI_NULL	0xc0
-#define PX_BRDCFG0_ELBC_DIU		0x02
-
-#define PX_BRDCFG1_DVIEN	0x80
-#define PX_BRDCFG1_DFPEN	0x40
-#define PX_BRDCFG1_BACKLIGHT	0x20
-
-#define PMUXCR_ELBCDIU_MASK	0xc0000000
-#define PMUXCR_ELBCDIU_NOR16	0x80000000
-#define PMUXCR_ELBCDIU_DIU	0x40000000
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register.  So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-/*
- * Variables used by the DIU/LBC switching code.  It's safe to makes these
- * global, because the DIU requires DDR, so we'll only run this code after
- * relocation.
- */
-static u8 px_brdcfg0;
-static u32 pmuxcr;
-static void *lbc_lcs0_ba;
-static void *lbc_lcs1_ba;
-static u32 old_br0, old_or0, old_br1, old_or1;
-static u32 new_br0, new_or0, new_br1, new_or1;
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	debug("DIU pixval = %u\n", pixval);
-
-	/* Modify PXCLK in GUTS CLKDVDR */
-	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
-	out_be32(&gur->clkdvdr, temp);			/* turn off clock */
-	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	const char *name;
-	u32 pixel_format;
-	u8 temp;
-	phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
-
-	/*
-	 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
-	 * otherwise writes to these addresses won't actually appear on the
-	 * local bus, and so the PIXIS won't see them.
-	 *
-	 * In FCM mode, writes go to the NAND controller, which does not pass
-	 * them to the localbus directly.  So we force BR0 and BR1 into GPCM
-	 * mode, since we don't care about what's behind the localbus any
-	 * more.  However, we save those registers first, so that we can
-	 * restore them when necessary.
-	 */
-	new_br0 = old_br0 = get_lbc_br(0);
-	new_br1 = old_br1 = get_lbc_br(1);
-	new_or0 = old_or0 = get_lbc_or(0);
-	new_or1 = old_or1 = get_lbc_or(1);
-
-	/*
-	 * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
-	 * force the values to simple 32KB GPCM windows with the most
-	 * conservative timing.
-	 */
-	if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
-		new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
-		new_or0 = OR_AM_32KB | 0xFF7;
-		set_lbc_br(0, new_br0);
-		set_lbc_or(0, new_or0);
-	}
-	if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
-		new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
-		new_or1 = OR_AM_32KB | 0xFF7;
-		set_lbc_br(1, new_br1);
-		set_lbc_or(1, new_or1);
-	}
-
-	/*
-	 * Determine the physical addresses for Chip Selects 0 and 1.  The
-	 * BR0/BR1 registers contain the truncated physical addresses for the
-	 * chip selects, mapped via the localbus LAW.  Since the BRx registers
-	 * only contain the lower 32 bits of the address, we have to determine
-	 * the upper 4 bits some other way.  The proper way is to scan the LAW
-	 * table looking for a matching localbus address. Instead, we cheat.
-	 * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
-	 * 36-bit addressing.
-	 */
-#ifdef CONFIG_PHYS_64BIT
-	phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
-	phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
-#else
-	phys0 = old_br0 & old_or0 & BR_BA;
-	phys1 = old_br1 & old_or1 & BR_BA;
-#endif
-
-	 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
-	lbc_lcs0_ba = map_physmem(phys0, 1, 0);
-	lbc_lcs1_ba = map_physmem(phys1, 1, 0);
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	temp = in_8(&pixis->brdcfg1);
-
-	if (strncmp(port, "lvds", 4) == 0) {
-		/* Single link LVDS */
-		temp &= ~PX_BRDCFG1_DVIEN;
-		/*
-		 * LVDS also needs backlight enabled, otherwise the display
-		 * will be blank.
-		 */
-		temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
-		name = "Single-Link LVDS";
-	} else {	/* DVI */
-		/* Enable the DVI port, disable the DFP and the backlight */
-		temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
-		temp |= PX_BRDCFG1_DVIEN;
-		name = "DVI";
-	}
-
-	printf("DIU:   Switching to %s monitor @ %ux%u\n", name, xres, yres);
-	out_8(&pixis->brdcfg1, temp);
-
-	/*
-	 * Enable PIXIS indirect access mode.  This is a hack that allows us to
-	 * access PIXIS registers even when the LBC pins have been muxed to the
-	 * DIU.
-	 */
-	setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
-	/*
-	 * Route the LAD pins to the DIU.  This will disable access to the eLBC,
-	 * which means we won't be able to read/write any NOR flash addresses!
-	 */
-	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-	px_brdcfg0 = in_8(lbc_lcs1_ba);
-	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
-	in_8(lbc_lcs1_ba);
-
-	/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
-	clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
-	pmuxcr = in_be32(&gur->pmuxcr);
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
-
-/*
- * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
- *
- * On the Freescale P1022, the DIU video signal and the LBC address/data lines
- * share the same pins, which means that when the DIU is active (e.g. the
- * console is on the DVI display), NOR flash cannot be accessed.  So we use the
- * weak accessor feature of the CFI flash code to temporarily switch the pin
- * mux from DIU to LBC whenever we want to read or write flash.  This has a
- * significant performance penalty, but it's the only way to make it work.
- *
- * There are two muxes: one on the chip, and one on the board. The chip mux
- * controls whether the pins are used for the DIU or the LBC, and it is
- * set via PMUXCR.  The board mux controls whether those signals go to
- * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
- */
-static int set_mux_to_lbc(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Switch the muxes only if they're currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		/*
-		 * In DIU mode, the PIXIS can only be accessed indirectly
-		 * since we can't read/write the LBC directly.
-		 */
-		/* Set the board mux to LBC.  This will disable the display. */
-		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-		out_8(lbc_lcs1_ba, px_brdcfg0);
-		in_8(lbc_lcs1_ba);
-
-		/* Disable indirect PIXIS mode */
-		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
-		clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
-
-		/* Set the chip mux to LBC mode, so that writes go to flash. */
-		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
-			 PMUXCR_ELBCDIU_NOR16);
-		in_be32(&gur->pmuxcr);
-
-		/* Restore the BR0 and BR1 settings */
-		set_lbc_br(0, old_br0);
-		set_lbc_or(0, old_or0);
-		set_lbc_br(1, old_br1);
-		set_lbc_or(1, old_or1);
-
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * set_mux_to_diu - re-enable the DIU muxing
- *
- * This function restores the chip and board muxing to point to the DIU.
- */
-static void set_mux_to_diu(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Set BR0 and BR1 to GPCM mode */
-	set_lbc_br(0, new_br0);
-	set_lbc_or(0, new_or0);
-	set_lbc_br(1, new_br1);
-	set_lbc_or(1, new_or1);
-
-	/* Enable indirect PIXIS mode */
-	setbits_8(&pixis->csr, PX_CTL_ALTACC);
-
-	/* Set the board mux to DIU.  This will enable the display. */
-	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
-	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
-	in_8(lbc_lcs1_ba);
-
-	/* Set the chip mux to DIU mode. */
-	out_be32(&gur->pmuxcr, pmuxcr);
-	in_be32(&gur->pmuxcr);
-}
-
-/*
- * pixis_read - board-specific function to read from the PIXIS
- *
- * This function overrides the generic pixis_read() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-u8 pixis_read(unsigned int reg)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Use indirect mode if the mux is currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		out_8(lbc_lcs0_ba, reg);
-		return in_8(lbc_lcs1_ba);
-	} else {
-		void *p = (void *)PIXIS_BASE;
-
-		return in_8(p + reg);
-	}
-}
-
-/*
- * pixis_write - board-specific function to write to the PIXIS
- *
- * This function overrides the generic pixis_write() function, so that it can
- * use PIXIS indirect mode if necessary.
- */
-void pixis_write(unsigned int reg, u8 value)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Use indirect mode if the mux is currently set to DIU mode */
-	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
-	    PMUXCR_ELBCDIU_NOR16) {
-		out_8(lbc_lcs0_ba, reg);
-		out_8(lbc_lcs1_ba, value);
-		/* Do a read-back to ensure the write completed */
-		in_8(lbc_lcs1_ba);
-	} else {
-		void *p = (void *)PIXIS_BASE;
-
-		out_8(p + reg, value);
-	}
-}
-
-void pixis_bank_reset(void)
-{
-	/*
-	 * For some reason, a PIXIS bank reset does not work if the PIXIS is
-	 * in indirect mode, so switch to direct mode first.
-	 */
-	set_mux_to_lbc();
-
-	out_8(&pixis->vctl, 0);
-	out_8(&pixis->vctl, 1);
-
-	while (1);
-}
-
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-void flash_write8(u8 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writeb(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write16(u16 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writew(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write32(u32 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-
-	__raw_writel(value, addr);
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.
-		 * set_mux_to_diu() includes a sync that will ensure the
-		 * __raw_readb() completes before it switches the mux.
-		 */
-		__raw_readb(addr);
-		set_mux_to_diu();
-	}
-}
-
-void flash_write64(u64 value, void *addr)
-{
-	int sw = set_mux_to_lbc();
-	uint32_t *p = addr;
-
-	/*
-	 * There is no __raw_writeq(), so do the write manually.  We don't trust
-	 * the compiler, so we use inline assembly.
-	 */
-	__asm__ __volatile__(
-		"stw%U0%X0 %2,%0;\n"
-		"stw%U1%X1 %3,%1;\n"
-		: "=m" (*p), "=m" (*(p + 1))
-		: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
-
-	if (sw) {
-		/*
-		 * To ensure the post-write is completed to eLBC, software must
-		 * perform a dummy read from one valid address from eLBC space
-		 * before changing the eLBC_DIU from NOR mode to DIU mode.  We
-		 * read addr+4 because we just wrote to addr+4, so that's how we
-		 * maintain execution order.  set_mux_to_diu() includes a sync
-		 * that will ensure the __raw_readb() completes before it
-		 * switches the mux.
-		 */
-		__raw_readb(addr + 4);
-		set_mux_to_diu();
-	}
-}
-
-u8 flash_read8(void *addr)
-{
-	u8 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readb(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u16 flash_read16(void *addr)
-{
-	u16 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readw(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u32 flash_read32(void *addr)
-{
-	u32 ret;
-
-	int sw = set_mux_to_lbc();
-
-	ret = __raw_readl(addr);
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-u64 flash_read64(void *addr)
-{
-	u64 ret;
-
-	int sw = set_mux_to_lbc();
-
-	/* There is no __raw_readq(), so do the read manually */
-	ret = *(volatile u64 *)addr;
-	if (sw)
-		set_mux_to_diu();
-
-	return ret;
-}
-
-#endif
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
deleted file mode 100644
index 079095d008..0000000000
--- a/board/freescale/p1022ds/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
deleted file mode 100644
index d10160d17a..0000000000
--- a/board/freescale/p1022ds/p1022ds.c
+++ /dev/null
@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-#include "../common/ngpixis.h"
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Set pmuxcr to allow both i2c1 and i2c2 */
-	setbits_be32(&gur->pmuxcr, 0x1000);
-#ifdef CONFIG_SYS_RAMBOOT
-	setbits_be32(&gur->pmuxcr,
-		in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-#endif
-
-	/* Read back the register to synchronize the write. */
-	in_be32(&gur->pmuxcr);
-
-	/* Set the pin muxing to enable ETSEC2. */
-	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
-
-	/* Enable the SPI */
-	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	u8 sw;
-
-	printf("Board: P1022DS Sys ID: 0x%02x, "
-	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
-	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
-
-	switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
-	case 0:
-		printf ("vBank: %u\n", ((sw & 0x30) >> 4));
-		break;
-	case 1:
-		printf ("NAND\n");
-		break;
-	case 2:
-	case 3:
-		puts ("Promjet\n");
-		break;
-	}
-
-	return 0;
-}
-
-#define CONFIG_TFP410_I2C_ADDR	0x38
-
-/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK	0x0c
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK	0x03
-
-/* Route the I2C1 pins to the SSI port instead. */
-#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI	0x08
-
-/* Choose the 12.288Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12		0x02
-
-/* Choose the 11.2896Mhz codec reference clock */
-#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11		0x01
-
-/* Connect to USB2 */
-#define CONFIG_PIXIS_BRDCFG0_USB2		0x10
-/* Connect to TFM bus */
-#define CONFIG_PIXIS_BRDCFG1_TDM		0x0c
-/* Connect to SPI */
-#define CONFIG_PIXIS_BRDCFG0_SPI		0x80
-
-int misc_init_r(void)
-{
-	u8 temp;
-	const char *audclk;
-	size_t arglen;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	/* For DVI, enable the TFP410 Encoder. */
-
-	temp = 0xBF;
-	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	debug("DVI Encoder Read: 0x%02x\n", temp);
-
-	temp = 0x10;
-	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
-		return -1;
-	debug("DVI Encoder Read: 0x%02x\n",temp);
-
-	/* Enable the USB2 in PMUXCR2 and FGPA */
-	if (hwconfig("usb2")) {
-		clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
-			MPC85xx_PMUXCR2_USB);
-		setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
-	}
-
-	/* tdm and audio can not enable simultaneous*/
-	if (hwconfig("tdm") && hwconfig("audclk")){
-		printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
-		return -1;
-	}
-
-	/* Enable the TDM in PMUXCR and FGPA */
-	if (hwconfig("tdm")) {
-		clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
-			MPC85xx_PMUXCR_TDM);
-		setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
-		/* TDM need some configration option by SPI */
-		clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
-			MPC85xx_PMUXCR_SPI);
-		setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
-	}
-
-	/*
-	 * Enable the reference clock for the WM8776 codec, and route the MUX
-	 * pins for SSI. The default is the 12.288 MHz clock
-	 */
-
-	if (hwconfig("audclk")) {
-		temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
-			CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
-		temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
-		audclk = hwconfig_arg("audclk", &arglen);
-		/* Check the first two chars only */
-		if (audclk && (strncmp(audclk, "11", 2) == 0))
-			temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
-		else
-			temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
-		setbits_8(&pixis->brdcfg1, temp);
-	}
-
-	return 0;
-}
-
-/*
- * A list of PCI and SATA slots
- */
-enum slot_id {
-	SLOT_PCIE1 = 1,
-	SLOT_PCIE2,
-	SLOT_PCIE3,
-	SLOT_PCIE4,
-	SLOT_PCIE5,
-	SLOT_SATA1,
-	SLOT_SATA2
-};
-
-/*
- * This array maps the slot identifiers to their names on the P1022DS board.
- */
-static const char *slot_names[] = {
-	[SLOT_PCIE1] = "Slot 1",
-	[SLOT_PCIE2] = "Slot 2",
-	[SLOT_PCIE3] = "Slot 3",
-	[SLOT_PCIE4] = "Slot 4",
-	[SLOT_PCIE5] = "Mini-PCIe",
-	[SLOT_SATA1] = "SATA 1",
-	[SLOT_SATA2] = "SATA 2",
-};
-
-/*
- * This array maps a given SERDES configuration and SERDES device to the PCI or
- * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
- */
-static u8 serdes_dev_slot[][SATA2 + 1] = {
-	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
-	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
-		   [PCIE2] = SLOT_PCIE5 },
-	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-		   [PCIE2] = SLOT_PCIE3,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
-		   [PCIE2] = SLOT_PCIE3 },
-	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
-		   [PCIE2] = SLOT_PCIE3,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x1c] = { [PCIE1] = SLOT_PCIE1,
-		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
-	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
-	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
-};
-
-
-/*
- * Returns the name of the slot to which the PCIe or SATA controller is
- * connected
- */
-const char *board_serdes_name(enum srds_prtcl device)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
-	const char *name = slot_names[slot];
-
-	if (name)
-		return name;
-	else
-		return "Nothing";
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	return 0;
-}
-
-/*
- * Initialize on-board and/or PCI Ethernet devices
- *
- * Returns:
- *      <0, error
- *       0, no ethernet devices found
- *      >0, number of ethernet devices initialized
- */
-int board_eth_init(bd_t *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	unsigned int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/**
- * ft_codec_setup - fix up the clock-frequency property of the codec node
- *
- * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option.  If audclk is not specified, then don't write anything
- * to the device tree, because it means that the codec clock is disabled.
- */
-static void ft_codec_setup(void *blob, const char *compatible)
-{
-	const char *audclk;
-	size_t arglen;
-	u32 freq;
-
-	audclk = hwconfig_arg("audclk", &arglen);
-	if (audclk) {
-		if (strncmp(audclk, "11", 2) == 0)
-			freq = 11289600;
-		else
-			freq = 12288000;
-
-		do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
-				       freq, 1);
-	}
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-	/* Update the WM8776 node's clock frequency property */
-	ft_codec_setup(blob, "wlf,wm8776");
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
deleted file mode 100644
index 39e1bee6f3..0000000000
--- a/board/freescale/p1022ds/spl.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/ngpixis.h"
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
-	66666000, 7499900, 83332500, 8999900,
-	99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
-	int px_spd;
-	u32 plat_ratio, sys_clk, bus_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	console_init_f();
-
-	/* Set pmuxcr to allow both i2c1 and i2c2 */
-	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
-	setbits_be32(&gur->pmuxcr,
-		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
-#ifdef CONFIG_SPL_SPI_BOOT
-	/* Enable the SPI */
-	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
-#endif
-
-	/* Read back the register to synchronize the write. */
-	in_be32(&gur->pmuxcr);
-
-	/* initialize selected port with appropriate baud rate */
-	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
-	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	bus_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
-	puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	puts("\nSPI Flash boot...\n");
-#endif
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
-	bd_t *bd;
-
-	memset(gd, 0, sizeof(gd_t));
-	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#ifndef CONFIG_SPL_NAND_BOOT
-	env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-#endif
-	/* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-#else
-	env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C
-	i2c_init_all();
-#else
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
-	puts("Tertiary program loader running in sram...");
-#else
-	puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
deleted file mode 100644
index 31de26318d..0000000000
--- a/board/freescale/p1022ds/spl_minimal.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-
-
-const static u32 sysclk_tbl[] = {
-	66666000, 7499900, 83332500, 8999900,
-	99999000, 11111000, 12499800, 13333200
-};
-
-void board_init_f(ulong bootflag)
-{
-	int px_spd;
-	u32 plat_ratio, sys_clk, bus_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-	/* for FPGA */
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-
-	/* initialize selected port with appropriate baud rate */
-	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
-	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	bus_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-			bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0,
-			CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	puts("\nSecond program loader running in sram...");
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
deleted file mode 100644
index 194fbd5afc..0000000000
--- a/board/freescale/p1022ds/tlb.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* W**G* - Flash/promjet, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
-	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
-	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
-	/* **** - eSDHC/eSPI/NAND boot */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 8, BOOKE_PAGESZ_1G, 1),
-	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_SYS_NAND_BASE
-	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_16K, 1),
-#endif
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 11, BOOKE_PAGESZ_256K, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);