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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2019-08-05 15:54:59 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-08 09:11:14 +0200 |
| commit | 26e054c943a7348904a8b432fc9a85185b0861c7 (patch) | |
| tree | e9fe6b1ff6f4f9e1907df5390b59bf07fe983766 /board/xilinx | |
| parent | 13210cd951046e828ecf3463f0087acbfb4f185e (diff) | |
| download | u-boot-26e054c943a7348904a8b432fc9a85185b0861c7.tar.gz u-boot-26e054c943a7348904a8b432fc9a85185b0861c7.tar.xz u-boot-26e054c943a7348904a8b432fc9a85185b0861c7.zip | |
arm64: versal: fpga: Add PL bit stream load support
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xilinx')
| -rw-r--r-- | board/xilinx/versal/board.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index b5ddd0c5ad..a2b00aa0b6 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -11,13 +11,23 @@ #include <asm/arch/hardware.h> #include <dm/device.h> #include <dm/uclass.h> +#include <versalpl.h> DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = XILINX_VERSAL_DESC; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif + return 0; } |