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authorStephen Warren <swarren@nvidia.com>2016-05-12 12:07:39 -0600
committerTom Warren <twarren@nvidia.com>2016-05-31 09:53:56 -0700
commit01a97a11db75c1a006da7b40d8ba4a325f05960c (patch)
treef2c49594d96073ee1f2020edc037f520805c4607 /board/toradex
parentda6e2fab5db000e31187aa4c9495c244011792c1 (diff)
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ARM: tegra: use DT bindings for GPIO naming
There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/toradex')
-rw-r--r--board/toradex/colibri_t20/colibri_t20.c6
-rw-r--r--board/toradex/colibri_t30/colibri_t30.c6
2 files changed, 6 insertions, 6 deletions
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 879f25a538..68fbf49579 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -103,11 +103,11 @@ void pin_mux_usb(void)
pinmux_tristate_disable(PMUX_PINGRP_DTE);
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PV4, "LAN_RESET");
- gpio_direction_output(GPIO_PV4, 0);
+ gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(V, 4), 0);
pinmux_tristate_disable(PMUX_PINGRP_GPV);
udelay(5);
- gpio_set_value(GPIO_PV4, 1);
+ gpio_set_value(TEGRA_GPIO(V, 4), 1);
/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 44b5beb928..e32362a93a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -47,8 +47,8 @@ void pinmux_init(void)
void pin_mux_usb(void)
{
/* Reset ASIX using LAN_RESET */
- gpio_request(GPIO_PDD0, "LAN_RESET");
- gpio_direction_output(GPIO_PDD0, 0);
+ gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+ gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
udelay(5);
- gpio_set_value(GPIO_PDD0, 1);
+ gpio_set_value(TEGRA_GPIO(DD, 0), 1);
}