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| author | Fabio Estevam <festevam@gmail.com> | 2019-03-21 10:59:06 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-03-31 19:54:56 +0200 |
| commit | 9b8d9ec41a6f161d53d32bf71f79332236b44ba1 (patch) | |
| tree | 7d5490964182b3cfba229a72726e17375337cf55 /board/technexion | |
| parent | 66c433ed4342e5761ee9b048c85fe47d31130b2e (diff) | |
| download | u-boot-9b8d9ec41a6f161d53d32bf71f79332236b44ba1.tar.gz u-boot-9b8d9ec41a6f161d53d32bf71f79332236b44ba1.tar.xz u-boot-9b8d9ec41a6f161d53d32bf71f79332236b44ba1.zip | |
pico-imx6ul: Fix eMMC boot after DM_MMC conversion
After the DM_MMC conversion the following eMMC boot error is observed:
U-Boot SPL 2019.04-rc4 (Mar 20 2019 - 18:53:28 +0000)
Trying to boot from MMC1
MMC Device 0 not found
spl: could not find mmc device 0. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
This happens because the SPL code does not initialize the SDHC pins
and clock.
Fix it by moving the original eMMC initialization from U-Boot proper
to SPL.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'board/technexion')
| -rw-r--r-- | board/technexion/pico-imx6ul/spl.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 6464a32d3b..f972cc9eaf 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -10,6 +10,7 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> +#include <fsl_esdhc.h> #include <linux/libfdt.h> #include <spl.h> @@ -141,4 +142,37 @@ void board_init_f(ulong dummy) void reset_cpu(ulong addr) { } + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} #endif |