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author | Vipin KUMAR <vipin.kumar@st.com> | 2010-01-15 19:15:51 +0530 |
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committer | Tom Rix <Tom.Rix@windriver.com> | 2010-01-23 08:15:50 -0600 |
commit | 4bfacad4e796f2e121ee7432705ecc9c61e7b6ca (patch) | |
tree | 4368c4edcb4d7a110638aaffcacd20e73a6d401d /board/spear | |
parent | 7e074158ce239380259c5fc97e87be2896169973 (diff) | |
download | u-boot-4bfacad4e796f2e121ee7432705ecc9c61e7b6ca.tar.gz u-boot-4bfacad4e796f2e121ee7432705ecc9c61e7b6ca.tar.xz u-boot-4bfacad4e796f2e121ee7432705ecc9c61e7b6ca.zip |
SPEAr : emi controller initialization for CFI driver support
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP
The standard CFI driver is used to interface with NOR flashes
Signed-off-by: Vipin <vipin.kumar@st.com>
Diffstat (limited to 'board/spear')
-rwxr-xr-x | board/spear/common/spr_misc.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 204ccf2edc..e35691200d 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -27,6 +27,7 @@ #include <net.h> #include <asm/io.h> #include <asm/arch/hardware.h> +#include <asm/arch/spr_emi.h> #include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h> @@ -83,6 +84,61 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + int spear_board_init(ulong mach_type) { struct xloader_table *xloader_tb = @@ -104,6 +160,9 @@ int spear_board_init(ulong mach_type) sizeof(chip->version)); } +#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif return 0; } |