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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-07-11 11:38:47 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-08-02 10:47:52 +0200 |
| commit | 361b715bbfbebc96d31c0ee48c34c2e66f049684 (patch) | |
| tree | 8d310c7f35ed210aceba13b5de5c1df020629dc9 /board/sbc8548/ddr.c | |
| parent | e6fc8995d6654df23387ccac91543a2206cfcb36 (diff) | |
| download | u-boot-361b715bbfbebc96d31c0ee48c34c2e66f049684.tar.gz u-boot-361b715bbfbebc96d31c0ee48c34c2e66f049684.tar.xz u-boot-361b715bbfbebc96d31c0ee48c34c2e66f049684.zip | |
imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 0 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/sbc8548/ddr.c')
0 files changed, 0 insertions, 0 deletions