S5PC2XX: Rename S5pc2XX to exynos

As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.

In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

9 files changed, 62 insertions, 62 deletions

diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index ddca1e21fc..0eebbfc244 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -1,5 +1,5 @@
 /*
- * Lowlevel setup for ORIGEN board based on S5PV310
+ * Lowlevel setup for ORIGEN board based on EXYNOS4210
  *
  * Copyright (C) 2011 Samsung Electronics
  *
@@ -43,11 +43,11 @@ lowlevel_init:
 
 	/* r5 has always zero */
 	mov	r5, #0
-	ldr	r7, =S5PC210_GPIO_PART1_BASE
-	ldr	r6, =S5PC210_GPIO_PART2_BASE
+	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
+	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
 
 	/* check reset status */
-	ldr	r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
+	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
 	ldr	r1, [r0]
 
 	/* AFTR wakeup reset */
@@ -97,9 +97,9 @@ wakeup_reset:
 
 exit_wakeup:
 	/* Load return address and jump to kernel */
-	ldr	r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
+	ldr	r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
 
-	/* r1 = physical address of s5pc210_cpu_resume function */
+	/* r1 = physical address of exynos4210_cpu_resume function */
 	ldr	r1, [r0]
 
 	/* Jump to kernel*/
@@ -113,7 +113,7 @@ exit_wakeup:
  */
 system_clock_init:
 	push	{lr}
-	ldr	r0, =S5PC210_CLOCK_BASE
+	ldr	r0, =EXYNOS4_CLOCK_BASE
 
 	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
 	ldr	r1, =CLK_SRC_CPU_VAL
@@ -290,13 +290,13 @@ uart_asm_init:
 
 	/* setup UART0-UART3 GPIOs (part1) */
 	mov	r0, r7
-	ldr	r1, =S5PC210_GPIO_A0_CON_VAL
-	str	r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
-	ldr	r1, =S5PC210_GPIO_A1_CON_VAL
-	str	r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
+	ldr	r1, =EXYNOS4_GPIO_A0_CON_VAL
+	str	r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
+	ldr	r1, =EXYNOS4_GPIO_A1_CON_VAL
+	str	r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
 
-	ldr r0, =S5PC210_UART_BASE
-	add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+	ldr r0, =EXYNOS4_UART_BASE
+	add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
 
 	ldr	r1, =ULCON_VAL
 	str	r1, [r0, #ULCON_OFFSET]
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
index a798848ba1..b49b193a79 100644
--- a/board/samsung/origen/mem_setup.S
+++ b/board/samsung/origen/mem_setup.S
@@ -1,5 +1,5 @@
 /*
- * Memory setup for ORIGEN board based on S5PV310
+ * Memory setup for ORIGEN board based on EXYNOS4210
  *
  * Copyright (C) 2011 Samsung Electronics
  *
@@ -38,7 +38,7 @@ mem_ctrl_asm_init:
 	str r1, [r0]
 
 #ifdef SET_MIU
-	ldr	r0, =S5PC210_MIU_BASE
+	ldr	r0, =EXYNOS4_MIU_BASE
 	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
 	ldr	r1, =0x20001507
 	str	r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
@@ -48,7 +48,7 @@ mem_ctrl_asm_init:
 	str	r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
 #endif
 	/* DREX0 */
-	ldr	r0, =S5PC210_DMC0_BASE
+	ldr	r0, =EXYNOS4_DMC0_BASE
 
 	/*
 	 * DLL Parameter Setting:
@@ -229,7 +229,7 @@ mem_ctrl_asm_init:
 	bne	8b
 
 	/* DREX1 */
-	ldr	r0, =S5PC210_DMC1_BASE	@0x10410000
+	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000
 
 	/*
 	 * DLL Parameter Setting:
@@ -410,11 +410,11 @@ mem_ctrl_asm_init:
 	bne	8b
 
 	/* turn on DREX0, DREX1 */
-	ldr	r0, =S5PC210_DMC0_BASE
+	ldr	r0, =EXYNOS4_DMC0_BASE
 	ldr	r1, =0x0FFF303a
 	str	r1, [r0, #DMC_CONCONTROL]
 
-	ldr	r0, =S5PC210_DMC1_BASE
+	ldr	r0, =EXYNOS4_DMC1_BASE
 	ldr	r1, =0x0FFF303a
 	str	r1, [r0, #DMC_CONCONTROL]
 
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index 8882646eca..638e7b1edb 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -27,13 +27,13 @@
 #include <asm/arch/mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
 
 int board_init(void)
 {
-	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
-	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
 
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 	return 0;
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 63d85d8a8c..d949ad27b8 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -98,8 +98,8 @@
 #define INFORM1_OFFSET			0x804
 
 /* GPIO Offsets for UART: GPIO Contol Register */
-#define S5PC210_GPIO_A0_CON_OFFSET	0x00
-#define S5PC210_GPIO_A1_CON_OFFSET	0x20
+#define EXYNOS4_GPIO_A0_CON_OFFSET	0x00
+#define EXYNOS4_GPIO_A1_CON_OFFSET	0x20
 
 /* UART Register offsets */
 #define ULCON_OFFSET		0x00
@@ -416,8 +416,8 @@
  * UART GPIO_A0/GPIO_A1 Control Register Value
  * 0x2: UART Function
  */
-#define S5PC210_GPIO_A0_CON_VAL	0x22222222
-#define S5PC210_GPIO_A1_CON_VAL	0x222222
+#define EXYNOS4_GPIO_A0_CON_VAL	0x22222222
+#define EXYNOS4_GPIO_A1_CON_VAL	0x222222
 
 /* ULCON: UART Line Control Value 8N1 */
 #define WORD_LEN_5_BIT		0x00
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
index 58b737bd12..7a1ea98aed 100644
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -1,5 +1,5 @@
 /*
- * Lowlevel setup for SMDKV310 board based on S5PC210
+ * Lowlevel setup for SMDKV310 board based on EXYNOS4210
  *
  * Copyright (C) 2011 Samsung Electronics
  *
@@ -45,11 +45,11 @@ lowlevel_init:
 
 	/* r5 has always zero */
 	mov	r5, #0
-	ldr	r7, =S5PC210_GPIO_PART1_BASE
-	ldr	r6, =S5PC210_GPIO_PART2_BASE
+	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
+	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
 
 	/* check reset status  */
-	ldr     r0, =(S5PC210_POWER_BASE + 0x81C)	@ INFORM7
+	ldr     r0, =(EXYNOS4_POWER_BASE + 0x81C)	@ INFORM7
 	ldr     r1, [r0]
 
 	/* AFTR wakeup reset */
@@ -95,9 +95,9 @@ wakeup_reset:
 
 exit_wakeup:
 	/* Load return address and jump to kernel */
-	ldr     r0, =(S5PC210_POWER_BASE + 0x800)	@ INFORM0
+	ldr     r0, =(EXYNOS4_POWER_BASE + 0x800)	@ INFORM0
 
-	/* r1 = physical address of s5pc210_cpu_resume function */
+	/* r1 = physical address of exynos4210_cpu_resume function */
 	ldr	r1, [r0]
 
 	/* Jump to kernel*/
@@ -111,7 +111,7 @@ exit_wakeup:
  */
 system_clock_init:
 	push	{lr}
-	ldr	r0, =S5PC210_CLOCK_BASE
+	ldr	r0, =EXYNOS4_CLOCK_BASE
 
 	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
 	ldr	r1, =0x0101
@@ -388,12 +388,12 @@ uart_asm_init:
 	/* setup UART0-UART3 GPIOs (part1) */
 	mov	r0, r7
 	ldr	r1, =0x22222222
-	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	str	r1, [r0, #0x00]			@ EXYNOS4_GPIO_A0_OFFSET
 	ldr	r1, =0x00222222
-	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+	str	r1, [r0, #0x20]			@ EXYNOS4_GPIO_A1_OFFSET
 
-	ldr r0, =S5PC210_UART_BASE
-	add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+	ldr r0, =EXYNOS4_UART_BASE
+	add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
 
 	ldr r1, =0x3C5
 	str	r1, [r0, #0x4]
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
index 73aebe3c60..d3b6265971 100644
--- a/board/samsung/smdkv310/mem_setup.S
+++ b/board/samsung/smdkv310/mem_setup.S
@@ -1,5 +1,5 @@
 /*
- * Memory setup for SMDKV310 board based on S5PC210
+ * Memory setup for SMDKV310 board based on EXYNOS4210
  *
  * Copyright (C) 2011 Samsung Electronics
  *
@@ -54,7 +54,7 @@ mem_ctrl_asm_init:
 	str r1, [r0]
 
 #ifdef SET_MIU
-	ldr	r0, =S5PC210_MIU_BASE	@0x10600000
+	ldr	r0, =EXYNOS4_MIU_BASE	@0x10600000
 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
 	ldr	r1, =0x0000000c
 	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
@@ -89,7 +89,7 @@ mem_ctrl_asm_init:
 #endif
 #endif
 	/* DREX0 */
-	ldr	r0, =S5PC210_DMC0_BASE	@0x10400000
+	ldr	r0, =EXYNOS4_DMC0_BASE	@0x10400000
 
 	ldr	r1, =0xe0000086
 	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
@@ -221,7 +221,7 @@ mem_ctrl_asm_init:
 	bne	8b
 
 	/* DREX1 */
-	ldr	r0, =S5PC210_DMC1_BASE	@0x10410000
+	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000
 
 	ldr	r1, =0xe0000086
 	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index d9caca7f18..81ac8f6f4a 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -29,8 +29,8 @@
 #include <asm/arch/sromc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
 
 static void smc9115_pre_init(void)
 {
@@ -52,8 +52,8 @@ static void smc9115_pre_init(void)
 
 int board_init(void)
 {
-	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
-	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
 
 	smc9115_pre_init();
 
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
index 67635bbfb2..dc7f69ea44 100644
--- a/board/samsung/universal_c210/lowlevel_init.S
+++ b/board/samsung/universal_c210/lowlevel_init.S
@@ -1,5 +1,5 @@
 /*
- * Lowlevel setup for universal board based on S5PC210
+ * Lowlevel setup for universal board based on EXYNOS4210
  *
  * Copyright (C) 2010 Samsung Electronics
  * Kyungmin Park <kyungmin.park@samsung.com>
@@ -43,11 +43,11 @@ lowlevel_init:
 	/* r5 has always zero */
 	mov	r5, #0
 
-	ldr	r7, =S5PC210_GPIO_PART1_BASE
-	ldr	r6, =S5PC210_GPIO_PART2_BASE
+	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
+	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
 
 	/* System Timer */
-	ldr	r0, =S5PC210_SYSTIMER_BASE
+	ldr	r0, =EXYNOS4_SYSTIMER_BASE
 	ldr	r1, =0x5000
 	str	r1, [r0, #0x0]
 	ldr	r1, =0xffffffff
@@ -57,7 +57,7 @@ lowlevel_init:
 
 	/* PMIC manual reset */
 	/* nPOWER: XEINT_23: GPX2[7] */
-	add	r0, r6, #0xC40			@ S5PC210_GPIO_X2_OFFSET
+	add	r0, r6, #0xC40			@ EXYNOS4_GPIO_X2_OFFSET
 	ldr	r1, [r0, #0x0]
 	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
 	orr	r1, r1, #(0x1 << 28)		@ Output
@@ -71,7 +71,7 @@ lowlevel_init:
 	bl	system_clock_init
 
 	/* Disable Watchdog */
-	ldr	r0, =S5PC210_WATCHDOG_BASE		@0x10060000
+	ldr	r0, =EXYNOS4_WATCHDOG_BASE		@0x10060000
 	str	r5, [r0]
 
 	/* UART */
@@ -99,12 +99,12 @@ uart_asm_init:
 	 */
 	mov	r0, r7
 	ldr	r1, =0x22222222
-	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	str	r1, [r0, #0x00]			@ EXYNOS4_GPIO_A0_OFFSET
 	ldr	r1, =0x00223322
-	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+	str	r1, [r0, #0x20]			@ EXYNOS4_GPIO_A1_OFFSET
 
-	/* UART_SEL GPY4[7] (part2) at S5PC210 */
-	add	r0, r6, #0x1A0			@ S5PC210_GPIO_Y4_OFFSET
+	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+	add	r0, r6, #0x1A0			@ EXYNOS4_GPIO_Y4_OFFSET
 	ldr	r1, [r0, #0x0]
 	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
 	orr	r1, r1, #(0x1 << 28)
@@ -125,7 +125,7 @@ uart_asm_init:
 	nop
 
 system_clock_init:
-	ldr	r0, =S5PC210_CLOCK_BASE
+	ldr	r0, =EXYNOS4_CLOCK_BASE
 
 	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
 	ldr	r1, =0x0101
@@ -326,7 +326,7 @@ system_clock_init:
 	nop
 
 system_power_init:
-	ldr	r0, =S5PC210_POWER_BASE		@ 0x10020000
+	ldr	r0, =EXYNOS4_POWER_BASE		@ 0x10020000
 
 	ldr	r2, =0x330C			@ PS_HOLD_CONTROL
 	ldr	r1, [r0, r2]
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index d767eaac49..f9b8a76429 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -31,8 +31,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
 unsigned int board_rev;
 
 u32 get_board_rev(void)
@@ -49,8 +49,8 @@ static void check_hw_revision(void);
 
 int board_init(void)
 {
-	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
-	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
 
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;