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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-06-16 01:16:50 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-06-16 04:27:28 +0200 |
| commit | c267952c41484dc1d8c73a7362bcabf33c8934e4 (patch) | |
| tree | 6e2760a49939b80167eca327d76acd5e84f4044e /board/renesas/eagle | |
| parent | 6d82ed8d37ac77b9c3bce9dc5844972d2e03218d (diff) | |
| download | u-boot-c267952c41484dc1d8c73a7362bcabf33c8934e4.tar.gz u-boot-c267952c41484dc1d8c73a7362bcabf33c8934e4.tar.xz u-boot-c267952c41484dc1d8c73a7362bcabf33c8934e4.zip | |
ARM: rmobile: Fix CPGW address on V3M Eagle
Fix the CPGWPR/CPGWPCR register address on V3M Eagle to unlock
access to the CPG clock control registers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/eagle')
| -rw-r--r-- | board/renesas/eagle/eagle.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index 4bf0a202e0..7b89c10cc7 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define CPGWPR 0xE6150900 #define CPGWPCR 0xE6150904 -#define CPGWPR 0xE615090C /* PLL */ #define PLL0CR 0xE61500D8 @@ -54,8 +54,9 @@ void s_init(void) int board_early_init_f(void) { - writel(0xA5A5FFFF, CPGWPCR); - writel(0x5A5A0000, CPGWPR); + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |