* Patch by Philippe Robin, 09 Mar 2004:

  Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
  Platform support.

* Patch by Masami Komiya, 08 Mar 2004:
  Don't overwrite server IP address or boot file name
  when the boot server does not return values

* Patch by listmember@orkun.us, 5 Mar 2004:
  Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC

6 files changed, 1067 insertions, 0 deletions

diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile
new file mode 100644
index 0000000000..00336aa779
--- /dev/null
+++ b/board/integratorap/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorap.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk
new file mode 100644
index 0000000000..df674917a5
--- /dev/null
+++ b/board/integratorap/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000 
+#
+
+TEXT_BASE = 0x01000000
diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c
new file mode 100644
index 0000000000..b120d63eb9
--- /dev/null
+++ b/board/integratorap/flash.c
@@ -0,0 +1,473 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
new file mode 100644
index 0000000000..960ec3a265
--- /dev/null
+++ b/board/integratorap/integratorap.c
@@ -0,0 +1,455 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+#   include <pci.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of Integrator Board */
+	gd->bd->bi_arch_number = 21;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	icache_enable ();
+
+	flash__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+	pci_init();
+#endif
+	setenv("verify", "n");
+	return (0);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifdef CONFIG_PCI
+
+#ifndef CONFIG_PCI_PNP
+
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+// V3 access routines
+#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
+#define _V3Read16(o)    (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
+
+#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
+#define _V3Read32(o)    (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
+
+// Compute address necessary to access PCI config space for the given
+// bus and device.
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
+    ({                                                                   		\
+    unsigned int __address, __devicebit;							\
+    unsigned short __mapaddress;								\
+    unsigned int __dev = PCI_DEV(__devfn);	/* FIXME to check!! (slot?) */	\
+											\
+    if (__bus == 0) {									\
+	/* local bus segment so need a type 0 config cycle */				\
+        /* build the PCI configuration "address" with one-hot in A31-A11 */		\
+        __address = PCI_CONFIG_BASE;							\
+        __address |= ((__devfn & 0x07) << 8);						\
+        __address |= __offset & 0xFF;							\
+        __mapaddress = 0x000A;    /* 101=>config cycle, 0=>A1=A0=0 */			\
+        __devicebit = (1 << (__dev + 11));						\
+											\
+        if ((__devicebit & 0xFF000000) != 0) {						\
+            /* high order bits are handled by the MAP register */			\
+            __mapaddress |= (__devicebit >> 16);					\
+        } else {									\
+            /* low order bits handled directly in the address */			\
+            __address |= __devicebit;							\
+        }										\
+    } else {	/* bus !=0 */								\
+        /* not the local bus segment so need a type 1 config cycle */			\
+        /* A31-A24 are don't care (so clear to 0) */					\
+        __mapaddress = 0x000B;    /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+        __address = PCI_CONFIG_BASE;							\
+        __address |= ((__bus & 0xFF) << 16);  	/* bits 23..16 = bus number 	*/	\
+        __address |= ((__dev & 0x1F) << 11);  	/* bits 15..11 = device number  */	\
+        __address |= ((__devfn & 0x07) << 8);  	/* bits 10..8  = function number*/	\
+        __address |= __offset & 0xFF;  		/* bits  7..0  = register number*/	\
+    }											\
+    _V3Write16(V3_LB_MAP1, __mapaddress);						\
+											\
+    __address;										\
+    })
+
+// _V3OpenConfigWindow - open V3 configuration window
+#define _V3OpenConfigWindow() 							\
+    {										\
+    /* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+    /* prefetchable), this frees up base1 for re-use by configuration*/		\
+    /* memory */								\
+										\
+    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
+			     0x90 | V3_LB_BASE_M_ENABLE));			\
+    /* Set up base1 to point into configuration space, note that MAP1 */	\
+    /* register is set up by pciMakeConfigAddress(). */				\
+										\
+    _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |		\
+			     0x40 | V3_LB_BASE_M_ENABLE));			\
+    }
+
+// _V3CloseConfigWindow - close V3 configuration window
+#define _V3CloseConfigWindow()							\
+    {										\
+    /* Reassign base1 for use by prefetchable PCI memory */			\
+    _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));		\
+    _V3Write16 (V3_LB_MAP1,							\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+										\
+    /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+										\
+    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
+			     0x80 | V3_LB_BASE_M_ENABLE));			\
+    }
+
+
+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
+				    int offset, unsigned char *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned short *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned int *val)
+{
+    _V3OpenConfigWindow();
+    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
+    *val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
+				     int offset,unsigned short val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
+				      int offset, unsigned int val)
+{
+    _V3OpenConfigWindow();
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
+    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
+    _V3CloseConfigWindow();
+
+    return 0;
+}
+
+/******************************
+ * PCI initialisation
+ ******************************/
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+    volatile int i, j;
+    struct pci_controller *hose = &integrator_hose;
+
+    /* setting this register will take the V3 out of reset */
+
+    *(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1;
+
+    /* wait a few usecs to settle the device and the PCI bus */
+
+    for (i = 0; i < 100 ; i++)
+	   j = i + 1;
+
+    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
+
+    do {
+        *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
+	*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
+    } while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
+	     *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
+
+    /* Make sure that V3 register access is not locked, if it is, unlock it */
+
+    if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+				== V3_SYSTEM_M_LOCK)
+	*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F;
+
+    /* Ensure that the slave accesses from PCI are disabled while we */
+    /* setup windows */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &=
+				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+
+    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+
+    *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
+
+    /* Make all accesses from PCI space retry until we're ready for them */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
+
+    /* Set up any V3 PCI Configuration Registers that we absolutely have to */
+    /* LB_CFG controls Local Bus protocol. */
+    /* Enable LocalBus byte strobes for READ accesses too. */
+    /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
+
+    /* PCI_CMD controls overall PCI operation. */
+    /* Enable PCI bus master. */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04;
+
+    /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
+					(V3_PCI_MAP_M_ADR_SIZE_512M |
+					V3_PCI_MAP_M_REG_EN |
+					V3_PCI_MAP_M_ENABLE);
+
+    /* PCI_BASE0 is the PCI address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
+
+    /* PCI_MAP1 is LOCAL address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
+			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
+			 V3_PCI_MAP_M_ENABLE);
+
+    /* PCI_BASE1 is the PCI address of the start of the window */
+
+    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
+
+    /* Set up the windows from local bus memory into PCI configuration, */
+    /* I/O and Memory. */
+    /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+
+    *(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) =
+			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0;
+
+    /* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+    /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+    /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+    /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+
+    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) =
+			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) =
+			((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+
+    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+
+    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) =
+			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+
+    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) =
+			(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+
+    /* Allow accesses to PCI Configuration space */
+    /* and set up A1, A0 for type 1 config cycles */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) =
+			((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) &
+			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
+			   V3_PCI_CFG_M_AD_LOW0;
+
+    /* now we can allow in PCI MEMORY accesses */
+
+    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
+
+    /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+    /* initialise and lock the V3 system register so that no one else */
+    /* can play with it */
+
+   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
+
+   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
+
+     /*
+      * Register the hose
+      */
+   hose->first_busno = 0;
+   hose->last_busno = 0xff;
+
+   /* System memory space */
+   pci_set_region(hose->regions + 0,
+		  0x00000000, 0x40000000, 0x01000000,
+		  PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+   /* PCI Memory - config space */
+   pci_set_region(hose->regions + 1,
+		  0x00000000, 0x62000000, 0x01000000,
+		  PCI_REGION_MEM);
+
+   /* PCI V3 regs */
+   pci_set_region(hose->regions + 2,
+		  0x00000000, 0x61000000, 0x00080000,
+		  PCI_REGION_MEM);
+
+   /* PCI I/O space */
+   pci_set_region(hose->regions + 3,
+		  0x00000000, 0x60000000, 0x00010000,
+		  PCI_REGION_IO);
+
+   pci_set_ops(hose,
+	       pci_integrator_read_byte,
+	       pci_integrator_read__word,
+	       pci_integrator_read_dword,
+	       pci_integrator_write_byte,
+	       pci_integrator_write_word,
+	       pci_integrator_write_dword);
+
+   hose->region_count = 4;
+
+   pci_register_hose(hose);
+
+   pciauto_config_init(hose);
+   pciauto_config_device(hose, 0);
+
+   hose->last_busno = pci_hose_scan(hose);
+}
+#endif
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
+
diff --git a/board/integratorap/platform.S b/board/integratorap/platform.S
new file mode 100644
index 0000000000..480e040cd0
--- /dev/null
+++ b/board/integratorap/platform.S
@@ -0,0 +1,33 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl platformsetup
+platformsetup:
+
+	/* All done by Integrator's boot monitor! */
+	mov pc, lr
diff --git a/board/integratorap/u-boot.lds b/board/integratorap/u-boot.lds
new file mode 100644
index 0000000000..da679c2e51
--- /dev/null
+++ b/board/integratorap/u-boot.lds
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+	. = ALIGN(4);
+	.bss : { *(.bss) }
+	armboot_end = .;
+}