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author | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
commit | a77034a8dfc7942ca08483138dccdebeacc36826 (patch) | |
tree | cecf2628651fb6fafd22ac7b9d6cd3f3770df2b6 /board/gdsys/gdppc440etx/init.S | |
parent | 500fbae2043532275e09a8666d837d052c9bad9a (diff) | |
parent | cf6eb6da433179674571f9370566b1ec8989a41a (diff) | |
download | u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.tar.gz u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.tar.xz u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.zip |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/gdsys/gdppc440etx/init.S')
-rw-r--r-- | board/gdsys/gdppc440etx/init.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S index 0bbd45a625..ba750cb538 100644 --- a/board/gdsys/gdppc440etx/init.S +++ b/board/gdsys/gdppc440etx/init.S @@ -51,25 +51,25 @@ tlbtab: * the speed up boot process. It is patched after relocation to enable SA_I */ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, - 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + 0, AC_RWX | SA_G/*|SA_I*/) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_R|AC_W|AC_X|SA_G ) + 0, AC_RWX | SA_G ) tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, - 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + 0, AC_RWX | SA_IG ) tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) /* PCI */ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, - 0, AC_R|AC_W|SA_G|SA_I ) + 0, AC_RW | SA_IG ) tlbtab_end |