diff options
| author | Tom Rini <trini@konsulko.com> | 2021-02-20 20:06:23 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-04-10 08:04:42 -0400 |
| commit | ce4ca2b7399f11b45ca3f8e1e856e5fa23c6f290 (patch) | |
| tree | a2b078a5896dff5ee2eadd384d300ace54955046 /board/gdsys/common | |
| parent | ddfb9aef65d5f109a62895f001cc1a6d70251361 (diff) | |
| download | u-boot-ce4ca2b7399f11b45ca3f8e1e856e5fa23c6f290.tar.gz u-boot-ce4ca2b7399f11b45ca3f8e1e856e5fa23c6f290.tar.xz u-boot-ce4ca2b7399f11b45ca3f8e1e856e5fa23c6f290.zip | |
ppc: Remove gdsys strider boards
These boards have not been converted to CONFIG_DM_MMC, along with other
DM conversions, by the deadline. Remove them.
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/gdsys/common')
| -rw-r--r-- | board/gdsys/common/Makefile | 4 | ||||
| -rw-r--r-- | board/gdsys/common/adv7611.c | 180 | ||||
| -rw-r--r-- | board/gdsys/common/adv7611.h | 12 | ||||
| -rw-r--r-- | board/gdsys/common/ch7301.c | 67 | ||||
| -rw-r--r-- | board/gdsys/common/ch7301.h | 12 |
5 files changed, 0 insertions, 275 deletions
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 7dfe104561..fa4c65c634 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -7,10 +7,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o -obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o -obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o -obj-$(CONFIG_STRIDER_CON) += osd.o -obj-$(CONFIG_STRIDER_CON_DP) += osd.o obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c deleted file mode 100644 index 06cdc05825..0000000000 --- a/board/gdsys/common/adv7611.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <i2c.h> - -#define ADV7611_I2C_ADDR 0x4c -#define ADV7611_RDINFO 0x2051 - -/* - * ADV7611 I2C Addresses in u-boot notation - */ -enum { - CP_I2C_ADDR = 0x22, - DPLL_I2C_ADDR = 0x26, - KSV_I2C_ADDR = 0x32, - HDMI_I2C_ADDR = 0x34, - EDID_I2C_ADDR = 0x36, - INFOFRAME_I2C_ADDR = 0x3e, - CEC_I2C_ADDR = 0x40, - IO_I2C_ADDR = ADV7611_I2C_ADDR, -}; - -/* - * Global Control Registers - */ -enum { - IO_RD_INFO_MSB = 0xea, - IO_RD_INFO_LSB = 0xeb, - IO_CEC_ADDR = 0xf4, - IO_INFOFRAME_ADDR = 0xf5, - IO_DPLL_ADDR = 0xf8, - IO_KSV_ADDR = 0xf9, - IO_EDID_ADDR = 0xfa, - IO_HDMI_ADDR = 0xfb, - IO_CP_ADDR = 0xfd, -}; - -int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C; - -int adv7611_probe(unsigned int screen) -{ - int old_bus = i2c_get_bus_num(); - unsigned int rd_info; - int res = 0; - - i2c_set_bus_num(adv7611_i2c[screen]); - - rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8) - | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB); - - if (rd_info != ADV7611_RDINFO) { - res = -1; - goto out; - } - - /* - * set I2C addresses to default values - */ - i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1); - i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1); - - /* - * do magic initialization sequence from - * "ADV7611 Register Settings Recommendations Revision 1.5" - * with most registers undocumented - */ - i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00); - i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03); - i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08); - i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f); - i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70); - i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda); - i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01); - i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98); - i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44); - - /* - * IO_REG_02, default 0xf0 - * - * INP_COLOR_SPACE (IO, Address 0x02[7:4]) - * default: 0b1111 auto - * set to : 0b0001 force RGB (range 0 to 255) input - * - * RGB_OUT (IO, Address 0x02[1]) - * default: 0 YPbPr color space output - * set to : 1 RGB color space output - */ - i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12); - - /* - * IO_REG_03, default 0x00 - * - * OP_FORMAT_SEL (IO, Address 0x03[7:0]) - * default: 0x00 8-bit SDR ITU-656 mode - * set to : 0x40 24-bit 4:4:4 SDR mode - */ - i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40); - - /* - * IO_REG_05, default 0x2c - * - * AVCODE_INSERT_EN (IO, Address 0x05[2]) - * default: 1 insert AV codes into data stream - * set to : 0 do not insert AV codes into data stream - */ - i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28); - - /* - * IO_REG_0C, default 0x62 - * - * POWER_DOWN (IO, Address 0x0C[5]) - * default: 1 chip is powered down - * set to : 0 chip is operational - */ - i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42); - - /* - * IO_REG_15, default 0xbe - * - * TRI_SYNCS (IO, Address 0x15[3) - * TRI_LLC (IO, Address 0x15[2]) - * TRI_PIX (IO, Address 0x15[1]) - * default: 1 video output pins are tristate - * set to : 0 video output pins are active - */ - i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0); - - /* - * HDMI_REGISTER_02H, default 0xff - * - * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0]) - * default: 1 disable termination - * set to : 0 enable termination - * Future options are: - * - use the chips automatic termination control - * - set this manually on cable detect - * but at the moment this seems a safe default. - */ - i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe); - - /* - * HDMI_CP_CNTRL_1, default 0x01 - * - * HDMI_FRUN_EN (CP, Address 0xBA[0]) - * default: 1 Enable the free run feature in HDMI mode - * set to : 0 Disable the free run feature in HDMI mode - */ - i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00); - - /* - * INT1_CONFIGURATION, default 0x20 - * - * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6]) - * default: 00 Interrupt signal is active for 4 Xtal periods - * set to : 11 Active until cleared - * - * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0]) - * default: 00 Open drain - * set to : 10 Drives high when active - */ - i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2); - -out: - i2c_set_bus_num(old_bus); - - return res; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h deleted file mode 100644 index 7b4e27c6bc..0000000000 --- a/board/gdsys/common/adv7611.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _ADV7611_H_ -#define _ADV7611_H_ - -int adv7611_probe(unsigned int screen); - -#endif diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c deleted file mode 100644 index 5e42467651..0000000000 --- a/board/gdsys/common/ch7301.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -/* Chrontel CH7301C DVI Transmitter */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <asm/io.h> -#include <errno.h> -#include <i2c.h> - -#define CH7301_I2C_ADDR 0x75 - -enum { - CH7301_CM = 0x1c, /* Clock Mode Register */ - CH7301_IC = 0x1d, /* Input Clock Register */ - CH7301_GPIO = 0x1e, /* GPIO Control Register */ - CH7301_IDF = 0x1f, /* Input Data Format Register */ - CH7301_CD = 0x20, /* Connection Detect Register */ - CH7301_DC = 0x21, /* DAC Control Register */ - CH7301_HPD = 0x23, /* Hot Plug Detection Register */ - CH7301_TCTL = 0x31, /* DVI Control Input Register */ - CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ - CH7301_TPD = 0x34, /* DVI PLL Divide Register */ - CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ - CH7301_TPF = 0x36, /* DVI PLL Filter Register */ - CH7301_TCT = 0x37, /* DVI Clock Test Register */ - CH7301_TSTP = 0x48, /* Test Pattern Register */ - CH7301_PM = 0x49, /* Power Management register */ - CH7301_VID = 0x4a, /* Version ID Register */ - CH7301_DID = 0x4b, /* Device ID Register */ - CH7301_DSP = 0x56, /* DVI Sync polarity Register */ -}; - -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; - -int ch7301_probe(unsigned screen, bool power) -{ - u8 value; - - i2c_set_bus_num(ch7301_i2c[screen]); - if (i2c_probe(CH7301_I2C_ADDR)) - return -1; - - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - if (value != 0x17) - return -1; - - if (power) { - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); - } else { - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01); - } - - return 0; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h deleted file mode 100644 index e0e8a9e9d4..0000000000 --- a/board/gdsys/common/ch7301.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _CH7301_H_ -#define _CH7301_H_ - -int ch7301_probe(unsigned screen, bool power); - -#endif |
