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| author | Tim Harvey <tharvey@gateworks.com> | 2015-04-08 12:54:54 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-04-22 14:39:11 +0200 |
| commit | 06edcb9d3787dc03ad6be87d083a7bcb15aa4c09 (patch) | |
| tree | b502ec75dc1e8e4c6bc6c9f6b5579391a58db9e2 /board/gateworks | |
| parent | eeca451ace0cdbac2e0c4bbc527fbe7488bdd4f9 (diff) | |
| download | u-boot-06edcb9d3787dc03ad6be87d083a7bcb15aa4c09.tar.gz u-boot-06edcb9d3787dc03ad6be87d083a7bcb15aa4c09.tar.xz u-boot-06edcb9d3787dc03ad6be87d083a7bcb15aa4c09.zip | |
imx: ventana: updated 16bit DDR calibration
Updated 16bit DDR calibration using values obtained from running the
i.MX6 DDR Stress Test tool over a set of boards over full operationg
temperature.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'board/gateworks')
| -rw-r--r-- | board/gateworks/gw_ventana/gw_ventana_spl.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 668e1122e8..baa2c6e00a 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -233,13 +233,15 @@ static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x001B0016, + .p0_mpwldectrl1 = 0x000C000E, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4324033A, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40403438, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40403D36, }; static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { @@ -255,13 +257,15 @@ static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x00420043, + .p0_mpwldectrl1 = 0x0016001A, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4238023B, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40404849, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40402E2F, }; static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { |