Merge branch 'next'

Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>

28 files changed, 26 insertions, 637 deletions

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index b0e109f0b8..04e04a6358 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_TARGET_P1022DS)		+= ics307_clk.o
 obj-$(CONFIG_P2020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
-obj-$(CONFIG_TARGET_P5020DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index 98b1adde62..e92b0d099d 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -28,21 +28,6 @@ source "board/freescale/common/Kconfig"
 
 endif
 
-if TARGET_P5020DS
-
-config SYS_BOARD
-	default "corenet_ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P5020DS"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
 if TARGET_P5040DS
 
 config SYS_BOARD
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 708e812e8e..e22cf703b7 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -6,22 +6,13 @@ F:	include/configs/P3041DS.h
 F:	configs/P3041DS_defconfig
 F:	configs/P3041DS_NAND_defconfig
 F:	configs/P3041DS_SDCARD_defconfig
-F:	configs/P3041DS_SECURE_BOOT_defconfig
 F:	configs/P3041DS_SPIFLASH_defconfig
 F:	configs/P3041DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P4080DS.h
 F:	configs/P4080DS_defconfig
 F:	configs/P4080DS_SDCARD_defconfig
-F:	configs/P4080DS_SECURE_BOOT_defconfig
 F:	configs/P4080DS_SPIFLASH_defconfig
 F:	configs/P4080DS_SRIO_PCIE_BOOT_defconfig
-F:	include/configs/P5020DS.h
-F:	configs/P5020DS_defconfig
-F:	configs/P5020DS_NAND_defconfig
-F:	configs/P5020DS_SDCARD_defconfig
-F:	configs/P5020DS_SECURE_BOOT_defconfig
-F:	configs/P5020DS_SPIFLASH_defconfig
-F:	configs/P5020DS_SRIO_PCIE_BOOT_defconfig
 F:	include/configs/P5040DS.h
 F:	configs/P5040DS_defconfig
 F:	configs/P5040DS_NAND_defconfig
@@ -33,5 +24,4 @@ CORENET_DS_SECURE_BOOT BOARD
 M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
-F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
 F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 98322b2747..4d62fc9ce1 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -8,9 +8,7 @@ obj-y	+= corenet_ds.o
 obj-y	+= ddr.o
 obj-$(CONFIG_TARGET_P3041DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P4080DS)	+= eth_p4080.o
-obj-$(CONFIG_TARGET_P5020DS)	+= eth_hydra.o
 obj-$(CONFIG_TARGET_P5040DS)	+= eth_superhydra.o
 obj-$(CONFIG_TARGET_P3041DS)	+= p3041ds_ddr.o
 obj-$(CONFIG_TARGET_P4080DS)	+= p4080ds_ddr.o
-obj-$(CONFIG_TARGET_P5020DS)	+= p5020ds_ddr.o
 obj-$(CONFIG_TARGET_P5040DS)	+= p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
deleted file mode 100644
index 112733be78..0000000000
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{0, 0, NULL}
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_1[] = {
-	{0, 0, NULL}
-};
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
deleted file mode 100644
index b09e409bbf..0000000000
--- a/board/freescale/corenet_ds/rcw_p5020ds.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for P5020DS.
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-0C540000 00000000 1E120000 00000000
-D8984A01 03002000 58000000 41000000
-00000000 00000000 00000000 10070000
-00000000 00000000 00000000 00000000
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
index c9f7fa3e2a..6e940dd875 100644
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ b/board/freescale/p1010rdb/MAINTAINERS
@@ -4,30 +4,18 @@ S:	Maintained
 F:	board/freescale/p1010rdb/
 F:	include/configs/P1010RDB.h
 F:	configs/P1010RDB-PA_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NAND_defconfig
-F:	configs/P1010RDB-PA_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_NOR_defconfig
-F:	configs/P1010RDB-PA_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PA_SDCARD_defconfig
 F:	configs/P1010RDB-PA_SPIFLASH_defconfig
-F:	configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NAND_defconfig
-F:	configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_NOR_defconfig
-F:	configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_36BIT_SDCARD_defconfig
 F:	configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NAND_defconfig
-F:	configs/P1010RDB-PB_NAND_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_NOR_defconfig
-F:	configs/P1010RDB-PB_NOR_SECBOOT_defconfig
 F:	configs/P1010RDB-PB_SDCARD_defconfig
 F:	configs/P1010RDB-PB_SPIFLASH_defconfig
-F:	configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index accf2f24e5..4c3a03e7cd 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
 
 	return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void fdt_del_flexcan(void *blob)
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 4ee4573d2b..fbaa6a6514 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -69,8 +69,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig
deleted file mode 100644
index 1e4cd10c6c..0000000000
--- a/board/freescale/p1023rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1023RDB
-
-config SYS_BOARD
-	default "p1023rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "P1023RDB"
-
-endif
diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS
deleted file mode 100644
index c06bac6d0d..0000000000
--- a/board/freescale/p1023rdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-P1023RDB BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/p1023rdb/
-F:	include/configs/P1023RDB.h
-F:	configs/P1023RDB_defconfig
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
deleted file mode 100644
index 78dc5d595a..0000000000
--- a/board/freescale/p1023rdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y	+= p1023rdb.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
deleted file mode 100644
index dc7a909e03..0000000000
--- a/board/freescale/p1023rdb/ddr.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-/* CONFIG_SYS_DDR_RAW_TIMING */
-/*
- * Hynix H5TQ1G83TFR-H9C
- */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 536870912u,
-	.capacity = 536870912u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 14,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1875,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 18000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
deleted file mode 100644
index 405fcd7b49..0000000000
--- a/board/freescale/p1023rdb/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
-		LAW_TRGT_IF_DPAA_SWP_SRAM),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
deleted file mode 100644
index b70ff6899a..0000000000
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Authors:  Roy Zang <tie-fei.zang@freescale.com>
- *           Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_portals.h>
-#include <fsl_qbman.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	/* Set ABSWP to implement conversion of addresses in the LBC */
-	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("Board: P1023 RDB\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	setup_qbman_portals();
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-	return gd->mem_clk;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-
-	/*
-	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
-	 * is not correct.
-	 */
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
-
-	fm_info_set_mdio(FM1_DTSEC1,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-	fm_info_set_mdio(FM1_DTSEC2,
-			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
-#ifdef CONFIG_FMAN_ENET
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-#endif
-	return 0;
-}
-#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
deleted file mode 100644
index 9f0314d190..0000000000
--- a/board/freescale/p1023rdb/tlb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_4M, 1),
-
-	/* W**G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_1M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_16K, 1),
-
-#ifdef CONFIG_SYS_RAMBOOT
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
-		      CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 12, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index 2f9640b67c..cd36150f63 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -1,10 +1,5 @@
-if TARGET_P1020MBG		|| \
-	TARGET_P1020RDB_PC	|| \
+if	TARGET_P1020RDB_PC	|| \
 	TARGET_P1020RDB_PD	|| \
-	TARGET_P1020UTM		|| \
-	TARGET_P1021RDB		|| \
-	TARGET_P1024RDB		|| \
-	TARGET_P1025RDB		|| \
 	TARGET_P2020RDB
 
 config SYS_BOARD
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index c2e924798e..b737b09b09 100644
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -3,10 +3,6 @@ P1_P2_RDB_PC BOARD
 S:	Maintained
 F:	board/freescale/p1_p2_rdb_pc/
 F:	include/configs/p1_p2_rdb_pc.h
-F:	configs/P1020MBG-PC_defconfig
-F:	configs/P1020MBG-PC_36BIT_defconfig
-F:	configs/P1020MBG-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020MBG-PC_SDCARD_defconfig
 F:	configs/P1020RDB-PC_defconfig
 F:	configs/P1020RDB-PC_36BIT_defconfig
 F:	configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -19,28 +15,6 @@ F:	configs/P1020RDB-PD_defconfig
 F:	configs/P1020RDB-PD_NAND_defconfig
 F:	configs/P1020RDB-PD_SDCARD_defconfig
 F:	configs/P1020RDB-PD_SPIFLASH_defconfig
-F:	configs/P1020UTM-PC_defconfig
-F:	configs/P1020UTM-PC_36BIT_defconfig
-F:	configs/P1020UTM-PC_36BIT_SDCARD_defconfig
-F:	configs/P1020UTM-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_defconfig
-F:	configs/P1021RDB-PC_36BIT_defconfig
-F:	configs/P1021RDB-PC_36BIT_NAND_defconfig
-F:	configs/P1021RDB-PC_36BIT_SDCARD_defconfig
-F:	configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
-F:	configs/P1021RDB-PC_NAND_defconfig
-F:	configs/P1021RDB-PC_SDCARD_defconfig
-F:	configs/P1021RDB-PC_SPIFLASH_defconfig
-F:	configs/P1024RDB_defconfig
-F:	configs/P1024RDB_36BIT_defconfig
-F:	configs/P1024RDB_NAND_defconfig
-F:	configs/P1024RDB_SDCARD_defconfig
-F:	configs/P1024RDB_SPIFLASH_defconfig
-F:	configs/P1025RDB_defconfig
-F:	configs/P1025RDB_36BIT_defconfig
-F:	configs/P1025RDB_NAND_defconfig
-F:	configs/P1025RDB_SDCARD_defconfig
-F:	configs/P1025RDB_SPIFLASH_defconfig
 F:	configs/P2020RDB-PC_defconfig
 F:	configs/P2020RDB-PC_36BIT_defconfig
 F:	configs/P2020RDB-PC_36BIT_NAND_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index b85cf0209e..86ff04e69d 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -4,10 +4,8 @@ P1_P2_RDB_PC represents a set of boards including
     P1020MSBG-PC
     P1020RDB-PC
     P1020RDB-PD
-    P1020UTM-PC
     P1021RDB-PC
     P1024RDB
-    P1025RDB
     P2020RDB-PC
 
 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 2346f6a0c2..be803ddf9c 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -14,9 +14,7 @@
 #include <asm/fsl_law.h>
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if	defined(CONFIG_P1020RDB_PROTO) || \
-	defined(CONFIG_TARGET_P1021RDB) || \
-	defined(CONFIG_TARGET_P1020UTM)
+#if	defined(CONFIG_P1020RDB_PROTO)
 /* Micron MT41J256M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,
@@ -146,8 +144,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif	defined(CONFIG_TARGET_P1024RDB) || \
-	defined(CONFIG_TARGET_P1025RDB)
+#elif	defined(CONFIG_TARGET_P1024RDB)
 /*
  * Samsung K4B2G0846C-HCH9
  * The following timing are for "downshift"
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b354f..4584f0147b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -45,68 +45,12 @@
 #define GPIO_SLIC_PIN		30
 #define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-#define GPIO_DDR_RST_PORT	1
-#define GPIO_DDR_RST_PIN	8
-#define GPIO_DDR_RST_DATA	(1 << (31 - GPIO_DDR_RST_PIN))
-
-#define GPIO_2BIT_MASK		(0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
-#endif
-
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-#define PCA_IOPORT_I2C_ADDR		0x23
-#define PCA_IOPORT_OUTPUT_CMD		0x2
-#define PCA_IOPORT_CFG_CMD		0x6
-#define PCA_IOPORT_QE_PIN_ENABLE	0xf8
-#define PCA_IOPORT_QE_TDM_ENABLE	0xf6
-#endif
-
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* GPIO */
 	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
-#endif
 	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
 	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
 	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
-
-#ifdef CONFIG_TARGET_P1025RDB
-	/* QE_MUX_MDC */
-	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
-
-	/* QE_MUX_MDIO */
-	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
-
-	/* UCC_1_MII */
-	{0, 23, 2, 0, 2}, /* CLK12 */
-	{0, 24, 2, 0, 1}, /* CLK9 */
-	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
-	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
-	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
-	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
-	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
-	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
-	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
-	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
-	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
-	{0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
-	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
-	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
-	{0, 17, 2, 0, 2}, /* ENET1_CRS    */
-	{0, 16, 2, 0, 2}, /* ENET1_COL    */
-
-	/* UCC_5_RMII */
-	{1, 11, 2, 0, 1}, /* CLK13 */
-	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
-	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
-	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
-	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
-	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
-	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
-	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
-#endif
-
 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 };
 #endif
@@ -156,16 +100,6 @@ void board_gpio_init(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
-	/* reset DDR3 */
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	udelay(1000);
-	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
-	/* disable CE_PB8 */
-	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
-#endif
 	/* Enable VSC7385 switch */
 	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
 
@@ -316,6 +250,10 @@ int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+	unsigned int vscfw_addr;
+	char *tmp;
+#endif
 
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -338,9 +276,24 @@ int board_early_init_r(void)
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+	/* If a VSC7385 microcode image is present, then upload it. */
+	tmp = env_get("vscfw_addr");
+	if (tmp) {
+		vscfw_addr = simple_strtoul(tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *)vscfw_addr,
+					    CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else {
+		puts("No address specified for VSC7385 microcode.\n");
+	}
+#endif
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 	struct fsl_pq_mdio_info mdio_info;
@@ -348,10 +301,6 @@ int board_eth_init(struct bd_info *bis)
 	ccsr_gur_t *gur __attribute__((unused)) =
 		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int num = 0;
-#ifdef CONFIG_VSC7385_ENET
-	char *tmp;
-	unsigned int vscfw_addr;
-#endif
 
 #ifdef CONFIG_TSEC1
 	SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +324,6 @@ int board_eth_init(struct bd_info *bis)
 		return 0;
 	}
 
-#ifdef CONFIG_VSC7385_ENET
-	/* If a VSC7385 microcode image is present, then upload it. */
-	tmp = env_get("vscfw_addr");
-	if (tmp) {
-		vscfw_addr = simple_strtoul(tmp, NULL, 16);
-		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
-		if (vsc7385_upload_firmware((void *) vscfw_addr,
-					CONFIG_VSC7385_IMAGE_SIZE))
-			puts("Failure uploading VSC7385 microcode.\n");
-	} else
-		puts("No address specified for VSC7385 microcode.\n");
-#endif
-
 	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 	mdio_info.name = DEFAULT_MII_NAME;
 
@@ -405,50 +341,6 @@ int board_eth_init(struct bd_info *bis)
 
 	return pci_eth_init(bis);
 }
-
-#if defined(CONFIG_QE) && \
-	(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
-static void fdt_board_fixup_qe_pins(void *blob)
-{
-	unsigned int oldbus;
-	u8 val8;
-	int node;
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	if (hwconfig("qe")) {
-		/* For QE and eLBC pins multiplexing,
-		 * there is a PCA9555 device on P1025RDB.
-		 * It control the multiplex pins' functions,
-		 * and setting the PCA9555 can switch the
-		 * function between QE and eLBC.
-		 */
-		oldbus = i2c_get_bus_num();
-		i2c_set_bus_num(0);
-		if (hwconfig("tdm"))
-			val8 = PCA_IOPORT_QE_TDM_ENABLE;
-		else
-			val8 = PCA_IOPORT_QE_PIN_ENABLE;
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
-				1, &val8, 1);
-		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
-				1, &val8, 1);
-		i2c_set_bus_num(oldbus);
-		/* if run QE TDM, Set ABSWP to implement
-		 * conversion of addresses in the eLBC.
-		 */
-		if (hwconfig("tdm")) {
-			set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
-			set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
-			setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-		}
-	} else {
-		node = fdt_path_offset(blob, "/qe");
-		if (node >= 0)
-			fdt_del_node(blob, node);
-	}
-
-	return;
-}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -478,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 			sizeof("okay"), 0);
-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
-	fdt_board_fixup_qe_pins(blob);
-#endif
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index e76c3e82c3..8aceceb56a 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 14971f0476..fcd7a55199 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -84,13 +84,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
-#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
 	/* 2G DDR on P1020MBG, map the second 1G */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* TARGET_P1020MBG */
+#endif
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da442fcc18..09dd88ac4e 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -103,8 +103,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index f83d69ba15..e7922954de 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -94,8 +94,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index c197884421..d8c2bbe28d 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -102,8 +102,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 07aab6349c..c64bd87115 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -72,8 +72,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 64d2753da8..9aa0a9b052 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd = (struct bd_info *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(struct bd_info));
 	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
 	arch_cpu_init();
 	get_clocks();