powerpc: Remove configs/MPC8536DS_36BIT_defconfig board

DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

8 files changed, 0 insertions, 599 deletions

diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig
deleted file mode 100644
index 1a6a9d4598..0000000000
--- a/board/freescale/mpc8536ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8536DS
-
-config SYS_BOARD
-	default "mpc8536ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8536DS"
-
-endif
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
deleted file mode 100644
index 5ce5164e49..0000000000
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8536DS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8536ds/
-F:	include/configs/MPC8536DS.h
-F:	configs/MPC8536DS_defconfig
-F:	configs/MPC8536DS_36BIT_defconfig
-F:	configs/MPC8536DS_SDCARD_defconfig
-F:	configs/MPC8536DS_SPIFLASH_defconfig
diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile
deleted file mode 100644
index 6b936aa299..0000000000
--- a/board/freescale/mpc8536ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= mpc8536ds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README
deleted file mode 100644
index 2a38bd6dda..0000000000
--- a/board/freescale/mpc8536ds/README
+++ /dev/null
@@ -1,127 +0,0 @@
-Overview:
-=========
-
-The MPC8536E integrates a PowerPC processor core with system logic
-required for imaging, networking, and communications applications.
-
-Boot from NAND:
-===============
-
-The MPC8536E is capable of booting from NAND flash which uses the image
-u-boot-nand.bin. This image contains two parts: a first stage image(also
-call 4K NAND loader and a second stage image. The former is appended to
-the latter to produce u-boot-nand.bin.
-
-The bootup process can be divided into two stages: the first stage will
-configure the L2SRAM, then copy the second stage image to L2SRAM and jump
-to it. The second stage image is to configure all the hardware and boot up
-to U-Boot command line.
-
-The 4K NAND loader's code comes from the corresponding nand_spl directory,
-along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
-is mainly used to shrink the code size to the 4K size limitation.
-
-The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
-second stage image. It's set in the board config file when boot from NAND
-is selected.
-
-Build and boot steps
---------------------
-
-1. Building image
-	make MPC8536DS_NAND_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 1011
-	SW9[1-3] = 101
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-3. Flash image
-	tftp 1000000 u-boot-nand.bin
-	nand erase 0 a0000
-	nand write 1000000 0 a0000
-
-Boot from On-chip ROM:
-======================
-
-The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
-and boot from eSPI. When power on, the porcessor excutes the ROM code to
-initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
-the memory device that interfaced to the controller, such as the SDCard or
-SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
-
-The memory device should contain a specific data structure with control word
-and config word at the fixed address. The config word direct the process how
-to config the memory device, and the control word direct the processor where
-to find the image on the memory device, or where copy the main image to. The
-user can use any method to store the data structure to the memory device, only
-if store it on the assigned address.
-
-Build and boot steps
---------------------
-
-For boot from eSDHC:
-1. Build image
-	make MPC8536DS_SDCARD_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 0111
-	SW3[1]   = 0
-	SW8[7]   = 0 - The on-board SD/MMC slot is active
-	SW8[7]   = 1 - The externel SD/MMC slot is active
-
-3. Put image to SDCard
-	Put the follwing info at the assigned address on the SDCard:
-
-	   Offset   |   Data     | Description
-	--------------------------------------------------------
-	| 0x40-0x43 | 0x424F4F54 | BOOT signature              |
-	--------------------------------------------------------
-	| 0x48-0x4B | 0x00080000 | u-boot.bin's size           |
-	--------------------------------------------------------
-	| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
-	--------------------------------------------------------
-	| 0x58-0x5B | 0xF8F80000 | Target Address              |
-	-------------------------------------------------------
-	| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address  |
-	--------------------------------------------------------
-	| 0x68-0x6B | 0x6        | Number of Config Addr/Data  |
-	--------------------------------------------------------
-	| 0x80-0x83 | 0xFF720100 | Config Addr 1               |
-	| 0x84-0x87 | 0xF8F80000 | Config Data 1               |
-	--------------------------------------------------------
-	| 0x88-0x8b | 0xFF720e44 | Config Addr 2               |
-	| 0x8c-0x8f | 0x0000000C | Config Data 2               |
-	--------------------------------------------------------
-	| 0x90-0x93 | 0xFF720000 | Config Addr 3               |
-	| 0x94-0x97 | 0x80010000 | Config Data 3               |
-	--------------------------------------------------------
-	| 0x98-0x9b | 0xFF72e40c | Config Addr 4               |
-	| 0x9c-0x9f | 0x00000040 | Config Data 4               |
-	--------------------------------------------------------
-	| 0xa0-0xa3 | 0x40000001 | Config Addr 5               |
-	| 0xa4-0xa7 | 0x00000100 | Config Data 5               |
-	--------------------------------------------------------
-	| 0xa8-0xab | 0x80000001 | Config Addr 6               |
-	| 0xac-0xaf | 0x80000001 | Config Data 6               |
-	--------------------------------------------------------
-	|              ......                                  |
-	--------------------------------------------------------
-	| 0x???????? | u-boot.bin                              |
-	--------------------------------------------------------
-
-	then insert the SDCard to the active slot to boot up.
-
-For boot from eSPI:
-1. Build image
-	make MPC8536DS_SPIFLASH_config
-	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
-
-2. Change dip-switch
-	SW2[5-8] = 0110
-
-3. Put image to SPI flash
-	Put the info in the above table onto the SPI flash, then
-	boot up.
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
deleted file mode 100644
index 8319ae8245..0000000000
--- a/board/freescale/mpc8536ds/ddr.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-
-	/*
-	 * For wake up arp feature, we need enable auto self refresh
-	 */
-	popts->auto_self_refresh_en = 1;
-	popts->sr_it = 0x6;
-}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
deleted file mode 100644
index d59b12d82c..0000000000
--- a/board/freescale/mpc8536ds/law.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
deleted file mode 100644
index 5907a7b428..0000000000
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ /dev/null
@@ -1,293 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <spd.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <spd_sdram.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-#include <sata.h>
-
-#include "../common/sgmii_riser.h"
-
-int board_early_init_f (void)
-{
-#ifdef CONFIG_MMC
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	setbits_be32(&gur->pmuxcr,
-			(MPC85xx_PMUXCR_SDHC_CD |
-			 MPC85xx_PMUXCR_SDHC_WP));
-
-	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
-	 * however, this erratum only applies to MPC8536 Rev1.0.
-	 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
-	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
-			(SVR_MIN(get_svr()) >= 0x1))
-			|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
-		setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
-#endif
-	return 0;
-}
-
-int checkboard (void)
-{
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf("Board: MPC8536DS Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
-		case PIXIS_VBOOT_LBMAP_NOR0:
-			puts ("vBank: 0\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR1:
-			puts ("vBank: 1\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR2:
-			puts ("vBank: 2\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR3:
-			puts ("vBank: 3\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_PJET:
-			puts ("Promjet\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NAND:
-			puts ("NAND\n");
-			break;
-	}
-
-	return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
-	uint d_init;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
-	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
-	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
-	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
-		udelay(1000);
-	}
-	debug("DDR: memory initialized\n\n");
-	asm("sync; isync");
-	udelay(500);
-#endif
-
-	return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno;
-
-	first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-
-	pci_speed = 66666000;
-	pci_32 = 1;
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 1;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].phyaddr = 0;
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (is_serdes_configured(SGMII_TSEC3)) {
-		puts("eTSEC3 is in sgmii mode.\n");
-		tsec_info[num].phyaddr = 1;
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	if (is_serdes_configured(SGMII_TSEC1) ||
-	    is_serdes_configured(SGMII_TSEC3)) {
-		fsl_sgmii_riser_init(tsec_info, num);
-	}
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-#ifdef CONFIG_HAS_FSL_MPH_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
deleted file mode 100644
index 5df4788e0a..0000000000
--- a/board/freescale/mpc8536ds/tlb.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-
-	/* W**G* - Flash/promjet, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256K, 1),
-
-	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);