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| author | Jian Li <jian.li@nxp.com> | 2020-01-20 15:14:42 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-07-14 15:23:46 +0800 |
| commit | 5865d14dde8f60f678e144e432a5e5ad223915d0 (patch) | |
| tree | b4aae596e1c3df20d7bcf0eed1f1437a6d079e46 /board/freescale | |
| parent | dd2f41370d8320f40944e80b2c87734a5ee1dc44 (diff) | |
| download | u-boot-5865d14dde8f60f678e144e432a5e5ad223915d0.tar.gz u-boot-5865d14dde8f60f678e144e432a5e5ad223915d0.tar.xz u-boot-5865d14dde8f60f678e144e432a5e5ad223915d0.zip | |
imx8mp: DDR performance tunning
1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/imx8mp_evk/lpddr4_timing.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index 6b17b3f141..75d6b530d2 100644 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -52,7 +52,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x68070707 }, { 0x3d40021c, 0xf08 }, - { 0x3d400250, 0x29001701 }, + { 0x3d400250, 0x00001705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, { 0x3d400264, 0x900093e7 }, |