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| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2015-03-20 17:08:54 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:24:04 -0700 |
| commit | 373762c34cd33b4a445b758090daaa87ccfa3fc6 (patch) | |
| tree | 448991328a7607ead530b1ea2ec9b3f6e716d755 /board/freescale/t4rdb/tlb.c | |
| parent | 0dc78ff857337a82d39d7e4390e317ffbc93097f (diff) | |
| download | u-boot-373762c34cd33b4a445b758090daaa87ccfa3fc6.tar.gz u-boot-373762c34cd33b4a445b758090daaa87ccfa3fc6.tar.xz u-boot-373762c34cd33b4a445b758090daaa87ccfa3fc6.zip | |
powerpc/t4rdb: Add SD boot support for T4240RDB board
This patch adds SD boot support for T4240RDB board. SPL
framework is used. PBL initializes the internal RAM and
copies SPL to it. Then SPL initializes DDR using SPD and
copies u-boot from SD card to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: Fix T4240RDB_SDCARD_defcofig]
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4rdb/tlb.c')
| -rw-r--r-- | board/freescale/t4rdb/tlb.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 474301e2a7..6a6b4b5cc1 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif + #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 18, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |