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author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-11-09 16:42:07 +0530 |
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committer | York Sun <yorksun@freescale.com> | 2015-11-30 08:53:04 -0800 |
commit | 449372148f6d9b5b8bded88ed8eee5c581a4bf81 (patch) | |
tree | 9e15d0812f5aebf6808e98c8d41c7a225f36b6fb /board/freescale/ls2080aqds/ls2080aqds_qixis.h | |
parent | 14480454c76d0f0bc4c5828cc1f054ba6278530e (diff) | |
download | u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.tar.gz u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.tar.xz u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.zip |
armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls2080aqds/ls2080aqds_qixis.h')
-rw-r--r-- | board/freescale/ls2080aqds/ls2080aqds_qixis.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/board/freescale/ls2080aqds/ls2080aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h new file mode 100644 index 0000000000..e281e5ffe0 --- /dev/null +++ b/board/freescale/ls2080aqds/ls2080aqds_qixis.h @@ -0,0 +1,30 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_QDS_QIXIS_H__ +#define __LS2_QDS_QIXIS_H__ + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 +#define BRDCFG9_SFPTX_MASK 0x10 +#define BRDCFG9_SFPTX_SHIFT 4 +#endif /*__LS2_QDS_QIXIS_H__*/ |