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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-03 18:41:30 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:50 -0700 |
| commit | ddd8a08052052561af38ecbe30930001a2ae940b (patch) | |
| tree | 711f459a403fcef66d00f90dba66026660524f82 /board/freescale/ls1043aqds | |
| parent | d9d9c977ec96ce74e558012ffda8ba590fcb9591 (diff) | |
| download | u-boot-ddd8a08052052561af38ecbe30930001a2ae940b.tar.gz u-boot-ddd8a08052052561af38ecbe30930001a2ae940b.tar.xz u-boot-ddd8a08052052561af38ecbe30930001a2ae940b.zip | |
armv8: fsl-layerscape: Organize SoC overview at common location
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1043aqds')
| -rw-r--r-- | board/freescale/ls1043aqds/README | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index a6fd7a35f5..913537d451 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -8,41 +8,8 @@ debugging environment. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043AQDS board Overview ----------------------- |