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| author | Ye Li <ye.li@nxp.com> | 2019-05-15 09:56:59 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-07-19 20:14:50 +0200 |
| commit | 9c1563e3fd24ca7161c089dfd999d031f95094de (patch) | |
| tree | 2427c80f845acaaaca1c198f46f06fa63c89a0c2 /board/cadence | |
| parent | 285aea01d2f9398b9c127c7a7fbaa401adf6969f (diff) | |
| download | u-boot-9c1563e3fd24ca7161c089dfd999d031f95094de.tar.gz u-boot-9c1563e3fd24ca7161c089dfd999d031f95094de.tar.xz u-boot-9c1563e3fd24ca7161c089dfd999d031f95094de.zip | |
mx7ulp: Select the SCG1 APLL PFD as a system clock source
Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/cadence')
0 files changed, 0 insertions, 0 deletions