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authorNicolas Ferre <nicolas.ferre@microchip.com>2019-08-08 07:48:26 +0000
committerEugen Hristev <eugen.hristev@microchip.com>2019-10-08 09:16:11 +0300
commit44b5c40be3dc4f063ec8bec1f3a71b1160e3788c (patch)
tree9f0070c78bade327c5b40f4039637fb4aee1a613 /board/atmel
parent00561e7d24e0d1986a6ed896003a03618a9ca17c (diff)
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board: atmel: add sama5d27_wlsom1_ek board
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Diffstat (limited to 'board/atmel')
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/Kconfig15
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/MAINTAINERS7
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/Makefile7
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c80
4 files changed, 109 insertions, 0 deletions
diff --git a/board/atmel/sama5d27_wlsom1_ek/Kconfig b/board/atmel/sama5d27_wlsom1_ek/Kconfig
new file mode 100644
index 0000000000..4b192b0849
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D27_WLSOM1_EK
+
+config SYS_BOARD
+ default "sama5d27_wlsom1_ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d27_wlsom1_ek"
+
+endif
diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
new file mode 100644
index 0000000000..59671ac540
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D27 WLSOM1 EK BOARD
+M: Nicolas Ferre <nicolas.ferre@microchip.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
+S: Maintained
+F: board/atmel/sama5d27_wlsom1_ek/
+F: include/configs/sama5d27_wlsom1_ek.h
+F: configs/sama5d27_wlsom1_ek_mmc_defconfig
diff --git a/board/atmel/sama5d27_wlsom1_ek/Makefile b/board/atmel/sama5d27_wlsom1_ek/Makefile
new file mode 100644
index 0000000000..cf827ae5e3
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+
+obj-y += sama5d27_wlsom1_ek.o
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
new file mode 100644
index 0000000000..483ec82900
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
+#endif
+ at91_pda_detect();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}