diff options
| author | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
| commit | a77034a8dfc7942ca08483138dccdebeacc36826 (patch) | |
| tree | cecf2628651fb6fafd22ac7b9d6cd3f3770df2b6 /board/amcc/luan/init.S | |
| parent | 500fbae2043532275e09a8666d837d052c9bad9a (diff) | |
| parent | cf6eb6da433179674571f9370566b1ec8989a41a (diff) | |
| download | u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.tar.gz u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.tar.xz u-boot-a77034a8dfc7942ca08483138dccdebeacc36826.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/amcc/luan/init.S')
| -rw-r--r-- | board/amcc/luan/init.S | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index 513b0fc560..06428d25ca 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -48,13 +48,13 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G) + tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) - tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) + tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) + tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) + tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) + tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) /* * TLB entries for SDRAM are not needed on this platform. @@ -63,12 +63,12 @@ tlbtab: */ /* internal ram (l2 cache) */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) /* peripherals at f0000000 */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) /* PCI */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) tlbtab_end |