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authorTom Rini <trini@konsulko.com>2021-04-11 14:11:05 -0400
committerTom Rini <trini@konsulko.com>2021-04-11 14:11:05 -0400
commit3b676a1662ac6b54d1e97ea40a0c41ee0925ffe3 (patch)
treed793c47b6ee68f30fb1426d526ac66f15b7cb636 /board/advantech/dms-ba16/clocks.cfg
parentc6a4ee2aaee541c12d290dd25561e771396817cc (diff)
parentd3cfc474b764fc9d8fca6dc1dfe56f42e564f0f5 (diff)
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Merge branch '2021-04-11-remove-non-migrated-boards'
- Remove a large number of boards that have not migrated to DM_MMC, for which the migration deadline with 2 years ago at v2019.04.
Diffstat (limited to 'board/advantech/dms-ba16/clocks.cfg')
-rw-r--r--board/advantech/dms-ba16/clocks.cfg25
1 files changed, 0 insertions, 25 deletions
diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg
deleted file mode 100644
index abc769c4e5..0000000000
--- a/board/advantech/dms-ba16/clocks.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en 1 --> CKO1 enabled
- * cko1_div 111 --> divide by 8
- * cko1_sel 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb