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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-07-15 21:47:52 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-07-21 12:45:10 +0200 |
| commit | cb20fe8f0b9ad9a9d48e243f7f72ab277b75a00f (patch) | |
| tree | 999d0eada0918cd931c9fecba9a3c4927f436c14 /arch | |
| parent | 285b3cb939a8f70d5233fd12e0b9f840eac53812 (diff) | |
| download | u-boot-cb20fe8f0b9ad9a9d48e243f7f72ab277b75a00f.tar.gz u-boot-cb20fe8f0b9ad9a9d48e243f7f72ab277b75a00f.tar.xz u-boot-cb20fe8f0b9ad9a9d48e243f7f72ab277b75a00f.zip | |
arm: socfpga: rst: add register definition for cold reset
This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Series changes: 2
- separate this patch to the register descriptions from the actual
sysreset driver patch
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 42beaecdd6..6ad037e325 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 /* |