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authorSimon Glass <sjg@chromium.org>2016-01-21 19:45:14 -0700
committerSimon Glass <sjg@chromium.org>2016-01-21 20:42:37 -0700
commit4f14d135f9924eb38990107f73f5b56afc8b41c8 (patch)
treecc4a279b591fc4e0b8a5c66b59fd1fe2409233ab /arch
parentf23cf909ee53a9284566f63e0a120bdfb9628561 (diff)
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rockchip: jerry: Fix the SDRAM timing
There is a minor error in the SDRAM timing. It does not seem to affect anything so far. Fix it just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/rk3288-veyron.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index a31e00eb5d..c201e855de 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -246,7 +246,7 @@
666000 1200000
>;
rockchip,num-channels = <2>;
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0