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| author | Marek Vasut <marex@denx.de> | 2018-08-06 21:47:50 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-08-13 22:35:42 +0200 |
| commit | 49e508e962df731590c3785af0d94493864c61ff (patch) | |
| tree | 7d34cc991f680217fba88bc9d774fe31fc1f3b52 /arch | |
| parent | 934aec71d6491ed3e5555f92255613dfdf402aa8 (diff) | |
| download | u-boot-49e508e962df731590c3785af0d94493864c61ff.tar.gz u-boot-49e508e962df731590c3785af0d94493864c61ff.tar.xz u-boot-49e508e962df731590c3785af0d94493864c61ff.zip | |
ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 59ede59b59..9f3c643df8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -42,9 +42,11 @@ int cm_wait_for_fsm(void) int set_cpu_clk_info(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Calculate the clock frequencies required for drivers */ cm_get_l4_sp_clk_hz(); cm_get_mmc_controller_clk_hz(); +#endif gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; |