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authorPeng Fan <peng.fan@nxp.com>2016-12-11 19:24:25 +0800
committerStefano Babic <sbabic@denx.de>2016-12-16 11:38:24 +0100
commit0e81982de08fc93118c3dc49cc81def0d3801445 (patch)
treeb221f86e0280526edfdd51d34d68f7a0b41aa023 /arch
parent40913fb595d1f909acbe098b3cbb076c8a635dda (diff)
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imx: mx6: fix mmdc ch0 clk for 6SL
>From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 299562884a..88f68f1137 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
+ if (is_mx6sl()) {
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+ break;
+ }
+
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0: