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| author | Bin Meng <bmeng.cn@gmail.com> | 2016-06-08 05:07:33 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-06-12 12:19:35 +0800 |
| commit | e264e3cc5be81548c6f102b6b597a474e5bd4f20 (patch) | |
| tree | 1e09d198f3863beb219780559191245a38f58d9f /arch/x86 | |
| parent | 8142340ee3847c6422294fad0f1adc01c9d27e2b (diff) | |
| download | u-boot-e264e3cc5be81548c6f102b6b597a474e5bd4f20.tar.gz u-boot-e264e3cc5be81548c6f102b6b597a474e5bd4f20.tar.xz u-boot-e264e3cc5be81548c6f102b6b597a474e5bd4f20.zip | |
x86: baytrail: Add 'reg' property in the pinctrl node
Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.
Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 5 | ||||
| -rw-r--r-- | arch/x86/dts/conga-qeval20-qa3-e3845.dts | 1 | ||||
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 1 |
3 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 4a50d8665e..536049b940 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,6 +65,11 @@ }; }; + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 1a4ecaad0e..7e69ba4873 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -30,6 +30,7 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; + reg = <0 0>; }; chosen { diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 936455b5e5..fda170cdd8 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -29,6 +29,7 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; + reg = <0 0>; /* GPIO E0 */ soc_gpio_s5_0@0 { |