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| author | Simon Glass <sjg@chromium.org> | 2015-03-26 09:29:29 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-18 11:11:15 -0600 |
| commit | 90b16d1491facd55909bdeca1326766dd5d0b925 (patch) | |
| tree | 4452fcddff86abfc0b92d275193aa5dfb39fe8ee /arch/x86/cpu | |
| parent | a274e9cac55de3c8ca4e877912a260fb646df38d (diff) | |
| download | u-boot-90b16d1491facd55909bdeca1326766dd5d0b925.tar.gz u-boot-90b16d1491facd55909bdeca1326766dd5d0b925.tar.xz u-boot-90b16d1491facd55909bdeca1326766dd5d0b925.zip | |
x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.
Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 13 |
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 2639ec2413..37f373148c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -142,7 +142,7 @@ int arch_cpu_init_dm(void) /* TODO(sjg@chromium.org): Get rid of gd->hose */ gd->hose = hose; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index c20e180329..bc1a0f06fb 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -510,7 +510,7 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev) pci_write_bar32(hose, dev, 3, 0x800); pci_write_bar32(hose, dev, 4, 0x900); - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; @@ -568,3 +568,14 @@ void lpc_enable(pci_dev_t dev) writew(0x0010, RCB_REG(DISPBDF)); setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); } + +static const struct udevice_id bd82x6x_lpc_ids[] = { + { .compatible = "intel,bd82x6x-lpc" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_lpc_drv) = { + .name = "lpc", + .id = UCLASS_LPC, + .of_match = bd82x6x_lpc_ids, +}; |