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| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:25 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:18 +0800 |
| commit | f45e747d6d0b107992e8aed74c001034c8a6f1a1 (patch) | |
| tree | 8f39a274ed8a75083893cf1899d64f242ab11059 /arch/x86/Kconfig | |
| parent | 2e2a0035d4ab520615fd13dc7c89a60a44eb6bc0 (diff) | |
| download | u-boot-f45e747d6d0b107992e8aed74c001034c8a6f1a1.tar.gz u-boot-f45e747d6d0b107992e8aed74c001034c8a6f1a1.tar.xz u-boot-f45e747d6d0b107992e8aed74c001034c8a6f1a1.zip | |
x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/Kconfig')
| -rw-r--r-- | arch/x86/Kconfig | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index bcce1114ce..44f7f0ab03 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -879,4 +879,20 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config INTEL_CAR_CQOS + bool "Support Intel Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up a portion of L2 cache for + CAR and use the remainder for actual caching. + +# +# Each bit in QOS mask controls this many bytes. This is calculated as: +# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS +# +config CACHE_QOS_SIZE_PER_BIT + hex + depends on INTEL_CAR_CQOS + default 0x20000 # 128 KB + endmenu |