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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-22 22:29:44 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-03 15:07:48 +0800 |
| commit | fd31e4fd184f9c203d16efed465e4ddeca1a79eb (patch) | |
| tree | becfdface86a3d232dbe5421c9beb00abd6fa849 /arch/riscv/lib | |
| parent | 1c17e55594a394ced7de88d91be294eaf8c564c1 (diff) | |
| download | u-boot-fd31e4fd184f9c203d16efed465e4ddeca1a79eb.tar.gz u-boot-fd31e4fd184f9c203d16efed465e4ddeca1a79eb.tar.xz u-boot-fd31e4fd184f9c203d16efed465e4ddeca1a79eb.zip | |
riscv: Do not build reset.c if SYSRESET is on
SYSRESET uclass driver already provides all the reset APIs, hence
exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b5e93244e0..6c503ff2b2 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o +ifeq ($(CONFIG_$(SPL_)SYSRESET),) obj-y += reset.o +endif obj-y += setjmp.o obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o |