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| author | Sean Anderson <seanga2@gmail.com> | 2020-06-24 06:41:19 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:22 +0800 |
| commit | b8bc120927a75ccbdd3a242555933dc644391bc8 (patch) | |
| tree | c45afd3e5baf6fe2c64ce1a35125eee0b240d313 /arch/riscv/lib | |
| parent | 40686c394e533fec765fe237936e353c84e73fff (diff) | |
| download | u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.tar.gz u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.tar.xz u-boot-b8bc120927a75ccbdd3a242555933dc644391bc8.zip | |
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/lib')
0 files changed, 0 insertions, 0 deletions