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| author | Anup Patel <anup@brainfault.org> | 2018-12-03 10:57:40 +0530 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-05 14:13:53 +0800 |
| commit | d2db2a8fa4f190d6d78ee7e9e642a180664cbccf (patch) | |
| tree | 065e64b9073f659188b32040bdaeba90dc33776b /arch/riscv/include | |
| parent | 2e2a2a5d4f0c2e2642326d9000ce1f1553632e6a (diff) | |
| download | u-boot-d2db2a8fa4f190d6d78ee7e9e642a180664cbccf.tar.gz u-boot-d2db2a8fa4f190d6d78ee7e9e642a180664cbccf.tar.xz u-boot-d2db2a8fa4f190d6d78ee7e9e642a180664cbccf.zip | |
riscv: Add kconfig option to run U-Boot in S-mode
This patch adds kconfig option RISCV_SMODE to run U-Boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.
It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.
In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/encoding.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce640..97cf906aa6 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -7,6 +7,12 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H +#ifdef CONFIG_RISCV_SMODE +#define MODE_PREFIX(__suffix) s##__suffix +#else +#define MODE_PREFIX(__suffix) m##__suffix +#endif + #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 |