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| author | Stefan Roese <sr@denx.de> | 2010-09-20 16:05:31 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-09-23 09:02:05 +0200 |
| commit | 550650ddd0fde00f245bc3da72d7272844198394 (patch) | |
| tree | 6a9ef8ac54cfaf5ff63a047b2c66d0e058e4cd9f /arch/powerpc/include/asm/ppc440epx_grx.h | |
| parent | afabb498b749b48ca3ee7e833fe1501e2d6993cb (diff) | |
| download | u-boot-550650ddd0fde00f245bc3da72d7272844198394.tar.gz u-boot-550650ddd0fde00f245bc3da72d7272844198394.tar.xz u-boot-550650ddd0fde00f245bc3da72d7272844198394.zip | |
ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.
The file 4xx_uart.c now only implements the UART clock calculation
function which also sets the SoC internal UART divisors.
All PPC4xx board config headers are changed to use this common NS16550
driver now.
Tested on these boards:
acadia, canyonlands, katmai, kilauea, sequoia, zeus
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/include/asm/ppc440epx_grx.h')
| -rw-r--r-- | arch/powerpc/include/asm/ppc440epx_grx.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index e0d7e3f6c2..252f35bdc6 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -30,9 +30,15 @@ */ /* Memory mapped registers */ -#define SPI0_MODE 0xef600090 -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00) -#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00) +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) /* DCR */ #define CPM0_ER 0x00b0 |