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| author | Steven A. Falco <sfalco@harris.com> | 2011-05-05 10:08:35 -0400 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-05-12 16:10:51 +0200 |
| commit | 644362c40aa8d356d2cc0d230ce0c3bad279c23c (patch) | |
| tree | 2f13f72006f88a509749e804bbc08864bb031f3e /arch/powerpc/include/asm/ppc405ex.h | |
| parent | 264eaa0ea967bac32214b87d60cfc86c8b22cac6 (diff) | |
| download | u-boot-644362c40aa8d356d2cc0d230ce0c3bad279c23c.tar.gz u-boot-644362c40aa8d356d2cc0d230ce0c3bad279c23c.tar.xz u-boot-644362c40aa8d356d2cc0d230ce0c3bad279c23c.zip | |
PPC405EX CHIP_21 erratum
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set. This patch implements the APM-proposed workaround.
To enable this patch for your board, add the appropriate define for your
CPU to your board header file. See kilauea.h for more information. The
following variants are supported:
#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.
Tested on custom boards using:
CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com>
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de>
Signed-off-by: Steve Falco <sfalco@harris.com>
Acked-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/include/asm/ppc405ex.h')
| -rw-r--r-- | arch/powerpc/include/asm/ppc405ex.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index 36d3149b8c..8070385816 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -43,6 +43,11 @@ #define SDR0_PFC1 0x4101 #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + #define SDR0_SDCS_SDD (0x80000000 >> 31) #define SDR0_SRST_DMC (0x80000000 >> 10) |