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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-09-21 14:59:05 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-24 08:27:44 -0400 |
| commit | 247921f966a94726de389b0a8b42e722e25fd09a (patch) | |
| tree | b7aa4b432504a8e25cba65fb75a3efeede3c8b3a /arch/powerpc/dts/pq3-etsec2-0.dtsi | |
| parent | 993c104dbea27e4ea7227bbef10e95e79df5909e (diff) | |
| download | u-boot-247921f966a94726de389b0a8b42e722e25fd09a.tar.gz u-boot-247921f966a94726de389b0a8b42e722e25fd09a.tar.xz u-boot-247921f966a94726de389b0a8b42e722e25fd09a.zip | |
dts: powerpc: p1020rdb: Add eTSEC DT nodes
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/pq3-etsec2-0.dtsi')
| -rw-r--r-- | arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; +}; + +ethernet@b0000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb0000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b0000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000 0x1000>; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; + }; +}; |