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| author | Scott Wood <scottwood@freescale.com> | 2014-03-26 20:30:56 -0500 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:47 -0700 |
| commit | 8d451a7129ee6820cc126c77f0f0a175a2cb2e8d (patch) | |
| tree | 84ce9c0b09a4ff7b3fbe735dd705a0da43920c05 /arch/powerpc/cpu | |
| parent | 44afbbc0f0733381fefa159cc14931d7f711356e (diff) | |
| download | u-boot-8d451a7129ee6820cc126c77f0f0a175a2cb2e8d.tar.gz u-boot-8d451a7129ee6820cc126c77f0f0a175a2cb2e8d.tar.xz u-boot-8d451a7129ee6820cc126c77f0f0a175a2cb2e8d.zip | |
powerpc/85xx: Fix e6500 L2 cache stash IDs
The value written to L2CSR1 didn't match the value written to the
device tree.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 33bc900167..31e63f7159 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ - if (reg && !((*reg) % 8)) + if (reg && !((*reg) % 8)) { + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg / 4) + 32 + 1); + } #else - if (reg) -#endif + if (reg) { fdt_setprop_cell(blob, l2_off, "cache-stash-id", - (*reg * 2) + 32 + 1); + (*reg * 2) + 32 + 1); + } +#endif #endif fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); |