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| author | Ying Zhang <b40530@freescale.com> | 2013-08-16 15:16:11 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-20 09:47:26 -0700 |
| commit | bb0dc1084f5dcf1dfd951d320c932d08bccbe429 (patch) | |
| tree | ba59aece0acb35211a67f503e25cac3111788fc4 /arch/powerpc/cpu/mpc85xx | |
| parent | 0151d99d74ec4b8a33133acf94ebcd25d717dfd7 (diff) | |
| download | u-boot-bb0dc1084f5dcf1dfd951d320c932d08bccbe429.tar.gz u-boot-bb0dc1084f5dcf1dfd951d320c932d08bccbe429.tar.xz u-boot-bb0dc1084f5dcf1dfd951d320c932d08bccbe429.zip | |
powerpc: mpc85xx: Support booting from SD Card with SPL
The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
ddr spd code can get the interleaving mode setting in env. It loads
final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions enabled.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 08188d75e5..85ec74ba94 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -44,6 +44,11 @@ SECTIONS } _edata = .; + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + . = ALIGN(8); __init_begin = .; __init_end = .; |