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authorStefano Babic <sbabic@denx.de>2016-06-18 10:24:54 +0200
committerStefano Babic <sbabic@denx.de>2016-06-18 10:25:13 +0200
commitdc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch)
treeec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /arch/powerpc/cpu/mpc85xx/start.S
parentd2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff)
parent6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff)
downloadu-boot-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.gz
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Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 82a151a0d0..4c51225868 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -720,16 +720,39 @@ enable_l2_cluster_l2:
ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
sync
stw r4, 0(r3) /* invalidate L2 */
+ /* Poll till the bits are cleared */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
bne 1b
+
+ /* L2PE must be set before L2 cache is enabled */
+ lis r4, (L2CSR0_L2PE)@h
+ ori r4, r4, (L2CSR0_L2PE)@l
+ sync
+ stw r4, 0(r3) /* enable L2 parity/ECC error checking */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
ori r4, r4, (L2CSR0_L2REP_MODE)@l
sync
stw r4, 0(r3) /* enable L2 */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif