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| author | Robert P. J. Day <rpjday@crashcourse.ca> | 2015-12-16 12:25:42 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-01-08 10:15:43 -0500 |
| commit | d7b4ca2b6f551c9de89292862216e365f7156ee0 (patch) | |
| tree | 8af7eb4c921479c962fcb2f2c6f548c340398c95 /arch/powerpc/cpu/mpc83xx/speed.c | |
| parent | f5abb40997eb68ef11102b726d8be747b3dd126e (diff) | |
| download | u-boot-d7b4ca2b6f551c9de89292862216e365f7156ee0.tar.gz u-boot-d7b4ca2b6f551c9de89292862216e365f7156ee0.tar.xz u-boot-d7b4ca2b6f551c9de89292862216e365f7156ee0.zip | |
powerpc: Various typo fixes under arch/powerpc/cpu/mpc83xx
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Diffstat (limited to 'arch/powerpc/cpu/mpc83xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/speed.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 1865626c21..2e91f51fce 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -170,7 +170,7 @@ int get_clocks(void) tsec1_clk = csb_clk / 3; break; default: - /* unkown SCCR_TSEC1CM value */ + /* unknown SCCR_TSEC1CM value */ return -2; } #endif @@ -191,7 +191,7 @@ int get_clocks(void) usbdr_clk = csb_clk / 3; break; default: - /* unkown SCCR_USBDRCM value */ + /* unknown SCCR_USBDRCM value */ return -3; } #endif @@ -212,7 +212,7 @@ int get_clocks(void) tsec2_clk = csb_clk / 3; break; default: - /* unkown SCCR_TSEC2CM value */ + /* unknown SCCR_TSEC2CM value */ return -4; } #elif defined(CONFIG_MPC8313) @@ -239,7 +239,7 @@ int get_clocks(void) usbmph_clk = csb_clk / 3; break; default: - /* unkown SCCR_USBMPHCM value */ + /* unknown SCCR_USBMPHCM value */ return -5; } @@ -266,7 +266,7 @@ int get_clocks(void) enc_clk = csb_clk / 3; break; default: - /* unkown SCCR_ENCCM value */ + /* unknown SCCR_ENCCM value */ return -7; } #endif @@ -286,7 +286,7 @@ int get_clocks(void) sdhc_clk = csb_clk / 3; break; default: - /* unkown SCCR_SDHCCM value */ + /* unknown SCCR_SDHCCM value */ return -8; } #endif @@ -305,7 +305,7 @@ int get_clocks(void) tdm_clk = csb_clk / 3; break; default: - /* unkown SCCR_TDMCM value */ + /* unknown SCCR_TDMCM value */ return -8; } #endif @@ -345,7 +345,7 @@ int get_clocks(void) pciexp1_clk = csb_clk / 3; break; default: - /* unkown SCCR_PCIEXP1CM value */ + /* unknown SCCR_PCIEXP1CM value */ return -9; } @@ -363,7 +363,7 @@ int get_clocks(void) pciexp2_clk = csb_clk / 3; break; default: - /* unkown SCCR_PCIEXP2CM value */ + /* unknown SCCR_PCIEXP2CM value */ return -10; } #endif @@ -383,7 +383,7 @@ int get_clocks(void) sata_clk = csb_clk / 3; break; default: - /* unkown SCCR_SATACM value */ + /* unknown SCCR_SATA1CM value */ return -11; } #endif @@ -413,7 +413,7 @@ int get_clocks(void) corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { - /* corecnf_tab_index is too high, possibly worng value */ + /* corecnf_tab_index is too high, possibly wrong value */ return -11; } switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { @@ -435,7 +435,7 @@ int get_clocks(void) core_clk = 3 * csb_clk; break; default: - /* unkown core to csb ratio */ + /* unknown core to csb ratio */ return -13; } |