diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-05-27 14:28:04 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 09:44:24 +0200 |
| commit | ace3be4f15875d74344336b9754c14274f940969 (patch) | |
| tree | 462b0bcc538f617028dbf06221cdeb26d2ce0c01 /arch/mips/lib | |
| parent | 83b0face8c710f719445f3c282c2ca6fad326bd7 (diff) | |
| download | u-boot-ace3be4f15875d74344336b9754c14274f940969.tar.gz u-boot-ace3be4f15875d74344336b9754c14274f940969.tar.xz u-boot-ace3be4f15875d74344336b9754c14274f940969.zip | |
MIPS: Move cache sizes to Kconfig
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/lib')
| -rw-r--r-- | arch/mips/lib/cache.c | 2 | ||||
| -rw-r--r-- | arch/mips/lib/cache_init.S | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 7482005b67..fbaafee8cd 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -9,7 +9,7 @@ #include <asm/cacheops.h> #include <asm/mipsregs.h> -#ifdef CONFIG_SYS_CACHELINE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO static inline unsigned long icache_line_size(void) { diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 08b7c3af52..4bb9a17e74 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -99,14 +99,14 @@ * */ LEAF(mips_cache_reset) -#ifdef CONFIG_SYS_ICACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t2, CONFIG_SYS_ICACHE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE #else l1_info t2, t8, MIPS_CONF1_IA_SHF #endif -#ifdef CONFIG_SYS_DCACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t3, CONFIG_SYS_DCACHE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE #else @@ -116,7 +116,7 @@ LEAF(mips_cache_reset) #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Determine the largest L1 cache size */ -#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE li v0, CONFIG_SYS_ICACHE_SIZE #else |