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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:50 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 4f9226b40379847339af8a7777be26f2db72e79b (patch) | |
| tree | a588a056dc8fd9167d595278f78f75553fd28a86 /arch/mips/cpu | |
| parent | 33b5c9b2092e10fa3b8b325823c846368f25bba9 (diff) | |
| download | u-boot-4f9226b40379847339af8a7777be26f2db72e79b.tar.gz u-boot-4f9226b40379847339af8a7777be26f2db72e79b.tar.xz u-boot-4f9226b40379847339af8a7777be26f2db72e79b.zip | |
MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/cpu')
| -rw-r--r-- | arch/mips/cpu/start.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 827a544987..6aec430a67 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -123,8 +123,9 @@ reset: mtc0 zero, CP0_COMPARE #ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED + mfc0 t0, CP0_CONFIG + and t0, t0, MIPS_CONF_IMPL + or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG #endif |