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authorTom Rini <trini@konsulko.com>2016-07-14 17:36:18 -0400
committerTom Rini <trini@konsulko.com>2016-07-14 17:36:18 -0400
commit3a592a1349ac3961b0f4f2db0a8d9f128225d897 (patch)
tree8b248a9332dc0cde9d8883377b24e4724ce0cf12 /arch/arm
parentb8e599746cac1833328bc3a8e37eeefe346baf90 (diff)
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Revert "armv8: Enable CPUECTLR.SMPEN for coherency"
Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv8/start.S8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index dfce469206..670e323b61 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,14 +81,6 @@ reset:
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
- /* Enalbe SMPEN bit for coherency.
- * This register is not architectural but at the moment
- * this bit should be set for A53/A57/A72.
- */
- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
- orr x0, x0, #0x40
- msr S3_1_c15_c2_1, x0
-
/* Apply ARM core specific erratas */
bl apply_core_errata