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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 20:07:40 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 22:42:00 +0900 |
| commit | d41b358fb331c2907f1f217686d38eeaf17eece4 (patch) | |
| tree | 9d8ea673b2beca4fab63764e762f74c455021e62 /arch/arm/mach-uniphier/sg-regs.h | |
| parent | c3d8f1e8e92fd70abb912942300cf44fff9e9d86 (diff) | |
| download | u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.tar.gz u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.tar.xz u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.zip | |
ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.
Turn the SG_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/sg-regs.h')
| -rw-r--r-- | arch/arm/mach-uniphier/sg-regs.h | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 39ffed5885..cba02d1f4a 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -10,15 +10,19 @@ #ifndef UNIPHIER_SG_REGS_H #define UNIPHIER_SG_REGS_H +#ifndef __ASSEMBLY__ +#include <linux/compiler.h> +#define sg_base ((void __iomem *)SG_BASE) +#endif + /* Base Address */ -#define SG_CTRL_BASE 0x5f800000 -#define SG_DBG_BASE 0x5f900000 +#define SG_BASE 0x5f800000 /* Revision */ -#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION 0x0000 /* Memory Configuration */ -#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF 0x0400 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) @@ -54,22 +58,22 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) -#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500) -#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) -#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) +#define SG_USBPHYCTRL 0x0500 +#define SG_ETPHYPSHUT 0x0554 +#define SG_ETPHYCNT 0x0550 /* Pin Control */ -#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) +#define SG_PINCTRL_BASE 0x1000 /* PH1-Pro4, PH1-Pro5 */ -#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) +#define SG_LOADPINCTRL 0x1700 /* Input Enable */ -#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) +#define SG_IECTRL 0x1d00 /* Pin Monitor */ -#define SG_PINMON0 (SG_DBG_BASE | 0x0100) -#define SG_PINMON2 (SG_DBG_BASE | 0x0108) +#define SG_PINMON0 0x00100100 +#define SG_PINMON2 0x00100108 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) |