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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 20:07:40 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-10 22:42:00 +0900 |
| commit | d41b358fb331c2907f1f217686d38eeaf17eece4 (patch) | |
| tree | 9d8ea673b2beca4fab63764e762f74c455021e62 /arch/arm/mach-uniphier/clk/pll-ld4.c | |
| parent | c3d8f1e8e92fd70abb912942300cf44fff9e9d86 (diff) | |
| download | u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.tar.gz u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.tar.xz u-boot-d41b358fb331c2907f1f217686d38eeaf17eece4.zip | |
ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.
Turn the SG_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/pll-ld4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-ld4.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 6a145a3baa..34f1c9cc28 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -16,7 +16,7 @@ static void upll_init(void) { u32 tmp, clk_mode_upll, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; @@ -56,7 +56,7 @@ static void vpll_init(void) { u32 tmp, clk_mode_axosel; - tmp = readl(SG_PINMON0); + tmp = readl(sg_base + SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; /* set 1 to VPLA27WP and VPLA27WP */ |