arm: socfpga: Rename Stratix10 and Agilex handoff common macros

Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

5 files changed, 57 insertions, 57 deletions

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 642dcbb0ac..e060e5754e 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -8,7 +8,7 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
-#include <asm/arch/handoff_s10.h>
+#include <asm/arch/handoff_soc64.h>
 #include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
deleted file mode 100644
index 3e9b606ce2..0000000000
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#ifndef _HANDOFF_S10_H_
-#define _HANDOFF_S10_H_
-
-/*
- * Offset for HW handoff from Quartus tools
- */
-#define S10_HANDOFF_BASE		0xFFE3F000
-#define S10_HANDOFF_MUX		(S10_HANDOFF_BASE + 0x10)
-#define S10_HANDOFF_IOCTL		(S10_HANDOFF_BASE + 0x1A0)
-#define S10_HANDOFF_FPGA		(S10_HANDOFF_BASE + 0x330)
-#define S10_HANODFF_DELAY		(S10_HANDOFF_BASE + 0x3F0)
-#define S10_HANDOFF_CLOCK		(S10_HANDOFF_BASE + 0x580)
-#define S10_HANDOFF_MISC		(S10_HANDOFF_BASE + 0x610)
-#define S10_HANDOFF_MAGIC_MUX	0x504D5558
-#define S10_HANDOFF_MAGIC_IOCTL	0x494F4354
-#define S10_HANDOFF_MAGIC_FPGA	0x46504741
-#define S10_HANDOFF_MAGIC_DELAY	0x444C4159
-#define S10_HANDOFF_MAGIC_CLOCK	0x434C4B53
-#define S10_HANDOFF_MAGIC_MISC	0x4D495343
-#define S10_HANDOFF_OFFSET_LENGTH	0x4
-#define S10_HANDOFF_OFFSET_DATA	0x10
-
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x608)
-#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x60C)
-#else
-#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x5fc)
-#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x600)
-#endif
-
-#define S10_HANDOFF_SIZE	4096
-
-#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
new file mode 100644
index 0000000000..804715b13d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _HANDOFF_SOC64_H_
+#define _HANDOFF_SOC64_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define SOC64_HANDOFF_BASE		0xFFE3F000
+#define SOC64_HANDOFF_MUX		(SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL		(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY		(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
+#define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MAGIC_MUX	0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL	0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
+#define SOC64_HANDOFF_OFFSET_LENGTH	0x4
+#define SOC64_HANDOFF_OFFSET_DATA	0x10
+
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x60C)
+#else
+#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x600)
+#endif
+
+#define SOC64_HANDOFF_SIZE	4096
+
+#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
index 0b497ec30c..d10fb5e454 100644
--- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -7,23 +7,23 @@
 #include <common.h>
 #include <errno.h>
 #include <asm/io.h>
-#include <asm/arch/handoff_s10.h>
+#include <asm/arch/handoff_soc64.h>
 
 static void sysmgr_pinmux_handoff_read(void *handoff_address,
 				       const u32 **table,
 				       unsigned int *table_len)
 {
 	unsigned int handoff_entry = (swab32(readl(handoff_address +
-					S10_HANDOFF_OFFSET_LENGTH)) -
-					S10_HANDOFF_OFFSET_DATA) /
+					SOC64_HANDOFF_OFFSET_LENGTH)) -
+					SOC64_HANDOFF_OFFSET_DATA) /
 					sizeof(unsigned int);
 	unsigned int handoff_chunk[handoff_entry], temp, i;
 
-	if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) {
+	if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) {
 		/* using handoff from Quartus tools if exists */
 		for (i = 0; i < handoff_entry; i++) {
 			temp = readl(handoff_address +
-				     S10_HANDOFF_OFFSET_DATA + (i * 4));
+				     SOC64_HANDOFF_OFFSET_DATA + (i * 4));
 			handoff_chunk[i] = swab32(temp);
 		}
 		*table = handoff_chunk;
@@ -33,24 +33,24 @@ static void sysmgr_pinmux_handoff_read(void *handoff_address,
 
 void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
 {
-	sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table,
+	sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table,
 				   table_len);
 }
 
 void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
 {
-	sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table,
+	sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table,
 				   table_len);
 }
 
 void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
 {
-	sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table,
+	sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table,
 				   table_len);
 }
 
 void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
 {
-	sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table,
+	sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table,
 				   table_len);
 }
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 049c5711a8..6a0d6b5ead 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -7,24 +7,24 @@
 #include <common.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/io.h>
-#include <asm/arch/handoff_s10.h>
+#include <asm/arch/handoff_soc64.h>
 #include <asm/arch/system_manager.h>
 
 const struct cm_config * const cm_get_default_config(void)
 {
 #ifdef CONFIG_SPL_BUILD
 	struct cm_config *cm_handoff_cfg = (struct cm_config *)
-		(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
+		(SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA);
 	u32 *conversion = (u32 *)cm_handoff_cfg;
 	u32 i;
-	u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
+	u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK);
 
-	if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
-		writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
+	if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) {
+		writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK);
 		for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
 			conversion[i] = swab32(conversion[i]);
 		return cm_handoff_cfg;
-	} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
+	} else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) {
 		return cm_handoff_cfg;
 	}
 #endif
@@ -35,7 +35,7 @@ const unsigned int cm_get_osc_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
 
-	u32 clock = readl(HANDOFF_CLOCK_OSC);
+	u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC);
 
 	writel(clock,
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
@@ -52,7 +52,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
 const unsigned int cm_get_fpga_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-	u32 clock = readl(HANDOFF_CLOCK_FPGA);
+	u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA);
 
 	writel(clock,
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);