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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-05-13 21:16:43 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-14 19:52:38 +0200 |
| commit | 430b42f76a4e50ffef7cc2b3c195ff645a438433 (patch) | |
| tree | 1897202a9687037fd357a5ece397ba23d09c381e /arch/arm/mach-socfpga/reset_manager_gen5.c | |
| parent | 90176e3be63802bc8630bab651d169993f0f0763 (diff) | |
| download | u-boot-430b42f76a4e50ffef7cc2b3c195ff645a438433.tar.gz u-boot-430b42f76a4e50ffef7cc2b3c195ff645a438433.tar.xz u-boot-430b42f76a4e50ffef7cc2b3c195ff645a438433.zip | |
arm: socfpga: remove re-added ad-hoc reset code
commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.
While at it, remove this function for gen5 as it should not be used.
Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager_gen5.c')
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_gen5.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 89a384b59c..9a32f5abfe 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -61,14 +61,6 @@ void socfpga_per_reset_all(void) writel(0xffffffff, &reset_manager_base->per2_mod_reset); } -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 |