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author | Kever Yang <kever.yang@rock-chips.com> | 2017-06-23 17:17:52 +0800 |
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committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-07-11 12:13:46 +0200 |
commit | 168eef7ada98c6bff53458013e42cdbc5adb3cd4 (patch) | |
tree | b1172b103a24b290219d9f5e65076c9f07346c08 /arch/arm/mach-rockchip/rk322x-board-spl.c | |
parent | b647442ce8a3c191677155ff29ca0c41dc8c6d0c (diff) | |
download | u-boot-168eef7ada98c6bff53458013e42cdbc5adb3cd4.tar.gz u-boot-168eef7ada98c6bff53458013e42cdbc5adb3cd4.tar.xz u-boot-168eef7ada98c6bff53458013e42cdbc5adb3cd4.zip |
rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch/arm/mach-rockchip/rk322x-board-spl.c')
-rw-r--r-- | arch/arm/mach-rockchip/rk322x-board-spl.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c new file mode 100644 index 0000000000..15216c74b0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/grf_rk322x.h> +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x11000000 +#define SGRF_BASE 0x10140000 + +#define DEBUG_UART_BASE 0x11030000 + +void board_debug_uart_init(void) +{ +static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("SPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + printf("timer init done\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) + back_to_bootrom(); +#endif +} |